HDLForge problem library

Hardware Design Practice Problems

Browse the complete HDLForge problem set. Each problem has its own crawlable page with the task, constraints, concepts and related practice, while the interactive editor remains available from HDLForge.

RTL Design

Study the RTL Design topic guide

2:1 MultiplexerEasy · Verilog / SystemVerilog / VHDL Parameterized CounterEasy · Verilog / SystemVerilog / VHDL Priority EncoderMedium · Verilog / SystemVerilog / VHDL Synchronous FIFOHard · Verilog / SystemVerilog / VHDL Shift RegisterEasy · Verilog / SystemVerilog / VHDL Rising Edge DetectorEasy · Verilog / SystemVerilog / VHDL 4-Request Priority ArbiterMedium · Verilog / SystemVerilog / VHDL Small Register FileMedium · Verilog / SystemVerilog / VHDL 8-bit LFSRMedium · Verilog / SystemVerilog / VHDL Programmable Clock DividerMedium · Verilog / SystemVerilog / VHDL Ready/Valid Skid BufferHard · Verilog / SystemVerilog / VHDL Elastic Pipeline RegisterMedium · Verilog / SystemVerilog / VHDL Asynchronous-Assert Reset SynchronizerMedium · Verilog / SystemVerilog / VHDL Binary to Gray CounterMedium · Verilog / SystemVerilog / VHDL Simple Dual-Port RAMMedium · Verilog / SystemVerilog / VHDL One-Hot Traffic-Light FSMMedium · Verilog / SystemVerilog / VHDL 3-to-8 DecoderEasy · Verilog / SystemVerilog / VHDL 4-Way One-Hot MultiplexerMedium · Verilog / SystemVerilog / VHDL 16-bit Magnitude ComparatorEasy · Verilog / SystemVerilog / VHDL 8-bit Barrel ShifterMedium · Verilog / SystemVerilog / VHDL Leading-Zero CounterMedium · Verilog / SystemVerilog / VHDL 8-bit Population CountMedium · Verilog / SystemVerilog / VHDL Four-Input Min/MaxMedium · Verilog / SystemVerilog / VHDL Even-Parity GeneratorEasy · Verilog / SystemVerilog / VHDL Register with Clock EnableEasy · Verilog / SystemVerilog / VHDL Toggle Flip-FlopEasy · Verilog / SystemVerilog / VHDL Sticky Status FlagEasy · Verilog / SystemVerilog / VHDL Pulse StretcherMedium · Verilog / SystemVerilog / VHDL 4-Cycle Delay LineMedium · Verilog / SystemVerilog / VHDL Serial-to-Parallel ReceiverMedium · Verilog / SystemVerilog / VHDL 1011 Sequence DetectorMedium · Verilog / SystemVerilog / VHDL Request/Acknowledge ControllerMedium · Verilog / SystemVerilog / VHDL Pedestrian Crossing FSMMedium · Verilog / SystemVerilog / VHDL Timeout and Retry FSMHard · Verilog / SystemVerilog / VHDL Packet Header Parser FSMHard · Verilog / SystemVerilog / VHDL Four-Beat Burst ControllerMedium · Verilog / SystemVerilog / VHDL Vending Machine FSMMedium · Verilog / SystemVerilog / VHDL Start/Busy/Done ControllerEasy · Verilog / SystemVerilog / VHDL Counted Synchronous FIFOHard · Verilog / SystemVerilog / VHDL FIFO Almost-Full / Almost-Empty FlagsMedium · Verilog / SystemVerilog / VHDL First-Word Fall-Through BufferHard · Verilog / SystemVerilog / VHDL FIFO Overflow / Underflow Sticky FlagsMedium · Verilog / SystemVerilog / VHDL Two-Entry Elastic BufferHard · Verilog / SystemVerilog / VHDL Packet FIFO Boundary TrackerMedium · Verilog / SystemVerilog / VHDL Circular Sample BufferMedium · Verilog / SystemVerilog / VHDL Single-Entry Bypass BufferHard · Verilog / SystemVerilog / VHDL RISC-V Program CounterEasy · SystemVerilog RISC-V Instruction DecoderEasy · SystemVerilog RISC-V Register FileMedium · SystemVerilog RISC-V Immediate GeneratorMedium · SystemVerilog RISC-V ALUMedium · SystemVerilog RISC-V Branch ControlMedium · SystemVerilog RISC-V Load/Store ControlMedium · SystemVerilog Integrate the 32-bit RISC-V CoreHard · SystemVerilog UART Baud Tick GeneratorEasy · SystemVerilog UART TX Frame ShifterEasy · SystemVerilog UART Transmit ControllerMedium · SystemVerilog UART RX Start-Bit DetectorEasy · SystemVerilog UART RX Data ShifterMedium · SystemVerilog UART Receive ControllerMedium · SystemVerilog Integrate the UART ControllerHard · SystemVerilog AXI-Lite Register BankEasy · SystemVerilog AXI-Lite AW Channel CaptureMedium · SystemVerilog AXI-Lite W Channel CaptureMedium · SystemVerilog AXI-Lite Write CommitMedium · SystemVerilog AXI-Lite B Response ChannelMedium · SystemVerilog AXI-Lite AR Channel CaptureMedium · SystemVerilog AXI-Lite R Response ChannelMedium · SystemVerilog Integrate the AXI4-Lite SlaveHard · SystemVerilog Async FIFO Dual-Port MemoryEasy · SystemVerilog Async FIFO Binary PointersMedium · SystemVerilog Binary-to-Gray Pointer ConversionEasy · SystemVerilog Synchronize Gray PointersMedium · SystemVerilog Async FIFO Empty DetectionEasy · SystemVerilog Async FIFO Full DetectionHard · SystemVerilog Per-Domain Reset SynchronizerMedium · SystemVerilog Integrate the Asynchronous FIFOHard · SystemVerilog IF/ID Pipeline RegisterMedium · SystemVerilog ID/EX Pipeline RegisterMedium · SystemVerilog EX Forwarding UnitHard · SystemVerilog Load-Use Hazard DetectorHard · SystemVerilog Branch Redirect and FlushMedium · SystemVerilog Writeback Result SelectEasy · SystemVerilog Pipeline Hazard Control IntegrationHard · SystemVerilog Cache Address DecodeMedium · SystemVerilog Cache Hit DetectionMedium · SystemVerilog Cache Line StoreHard · SystemVerilog Cache Miss / Refill FSMHard · SystemVerilog Four-Beat Refill CounterMedium · SystemVerilog Direct-Mapped Cache ControllerHard · SystemVerilog 2-bit Saturating CounterEasy · SystemVerilog Branch History TableMedium · SystemVerilog Branch Target BufferHard · SystemVerilog Predicted Next-PC SelectEasy · SystemVerilog Misprediction DetectionMedium · SystemVerilog Branch Predictor TopHard · SystemVerilog SoC Address DecoderMedium · SystemVerilog Boot ROMEasy · SystemVerilog Word-Addressed Data RAMMedium · SystemVerilog Memory-Mapped GPIOMedium · SystemVerilog Machine Timer PeripheralMedium · SystemVerilog Interrupt ControllerMedium · SystemVerilog Small RISC-V SoC IntegrationHard · SystemVerilog Vector Register FileMedium · SystemVerilog SIMD Execute Pipeline RegisterEasy · SystemVerilog DMA Control RegistersMedium · SystemVerilog DMA Address GeneratorMedium · SystemVerilog DMA Read ChannelHard · SystemVerilog DMA Write ChannelHard · SystemVerilog DMA Transfer CounterMedium · SystemVerilog DMA Transfer ControllerHard · SystemVerilog AXI Crossbar Address DecoderMedium · SystemVerilog Two-Master Round-Robin ArbiterMedium · SystemVerilog AXI Request RouterHard · SystemVerilog AXI Write Ownership LockHard · SystemVerilog AXI Response RouterHard · SystemVerilog AXI Decode Error ResponderMedium · SystemVerilog 2x3 AXI-Lite Crossbar TopHard · SystemVerilog Peripheral Reset ControllerMedium · SystemVerilog APB Peripheral DecoderMedium · SystemVerilog APB Read/Response MultiplexerMedium · SystemVerilog APB GPIO PeripheralMedium · SystemVerilog APB Timer PeripheralMedium · SystemVerilog UART Register BlockMedium · SystemVerilog APB Peripheral Subsystem TopHard · SystemVerilog I²C START / STOP DetectorMedium · SystemVerilog I²C Address MatcherEasy · SystemVerilog I²C Byte ReceiverMedium · SystemVerilog I²C ACK / NACK DriverMedium · SystemVerilog I²C Byte TransmitterMedium · SystemVerilog I²C Register PointerMedium · SystemVerilog I²C Clock-Stretch ControlEasy · SystemVerilog Memory-Mapped I²C Register SlaveHard · SystemVerilog

SystemVerilog

Study the SystemVerilog topic guide

always_comb vs always_ffEasy · SystemVerilog SystemVerilog InterfaceMedium · SystemVerilog Clock and Reset GeneratorEasy · SystemVerilog Reusable Stimulus TaskEasy · SystemVerilog Self-Checking Adder TestbenchEasy · SystemVerilog Queue-Based Expected-Value CheckerMedium · SystemVerilog Randomized RTL Stimulus LoopMedium · SystemVerilog Simulation Timeout WatchdogEasy · SystemVerilog File-Driven Test VectorsMedium · SystemVerilog Fixed-Latency Pipeline CheckerMedium · SystemVerilog Backpressure-Aware Stream DriverMedium · SystemVerilog Interface ModportsMedium · SystemVerilog Interface Clocking BlockMedium · SystemVerilog Monitor-Only Interface ModportEasy · SystemVerilog Parameterized Bus InterfaceMedium · SystemVerilog Constrain Address RangeEasy · SystemVerilog Weighted Random DistributionMedium · SystemVerilog Solve-Before ConstraintMedium · SystemVerilog Unique Random Byte ArrayMedium · SystemVerilog Basic Coverpoint BinsEasy · SystemVerilog Cross Operation and SizeMedium · SystemVerilog Illegal Coverage BinMedium · SystemVerilog Ignore Uninteresting Coverage RangeEasy · SystemVerilog State Transition CoverageMedium · SystemVerilog

SVA

Study the SVA topic guide

Valid Must Eventually HandshakeMedium · SystemVerilog Reset Clears StateEasy · SystemVerilog Payload Stable While StalledMedium · SystemVerilog One-Hot Grant AssertionEasy · SystemVerilog No FIFO Overflow AssertionEasy · SystemVerilog No FIFO Underflow AssertionEasy · SystemVerilog Bounded Request ResponseMedium · SystemVerilog Mutual Exclusion AssertionEasy · SystemVerilog One-Cycle Pulse WidthMedium · SystemVerilog AXI-Lite Protocol AssertionsHard · SystemVerilog RISC-V Core AssertionsHard · SystemVerilog AXI Crossbar Protocol AssertionsHard · SystemVerilog

UVM

Study the UVM topic guide

Build a UVM DriverMedium · SystemVerilog Reference Model ScoreboardHard · SystemVerilog UVM Sequence ItemMedium · SystemVerilog UVM Sequence BodyMedium · SystemVerilog UVM Monitor Analysis PortMedium · SystemVerilog UVM Agent Build and ConnectHard · SystemVerilog UVM Config DB Virtual InterfaceMedium · SystemVerilog UVM Test ObjectionsEasy · SystemVerilog AXI-Lite Verification InterfaceMedium · SystemVerilog AXI-Lite Sequence ItemMedium · SystemVerilog AXI-Lite UVM DriverHard · SystemVerilog AXI-Lite UVM MonitorHard · SystemVerilog AXI-Lite Reference ScoreboardHard · SystemVerilog AXI-Lite Functional CoverageMedium · SystemVerilog RISC-V Instruction TransactionMedium · SystemVerilog Constrained RV32I Instruction SequenceHard · SystemVerilog AXI Crossbar Sequence ItemMedium · SystemVerilog Constrained Crossbar Traffic SequenceHard · SystemVerilog AXI Crossbar MonitorMedium · SystemVerilog Crossbar Contention SequenceHard · SystemVerilog

Protocols

Study the Protocols topic guide

UART TransmitterMedium · Verilog / SystemVerilog / VHDL SPI MasterHard · Verilog / SystemVerilog / VHDL Backpressure-Safe Ready/Valid SourceMedium · Verilog / SystemVerilog / VHDL APB Register PeripheralHard · Verilog / SystemVerilog / VHDL AXI-Lite Write Register SlaveHard · Verilog / SystemVerilog / VHDL

FPGA

Study the FPGA topic guide

Button DebouncerEasy · Verilog / SystemVerilog / VHDL Traffic Light FSMEasy · Verilog / SystemVerilog / VHDL Parameterized PWM GeneratorEasy · Verilog / SystemVerilog / VHDL Toggle-Based Pulse SynchronizerHard · Verilog / SystemVerilog / VHDL Clock-Enable Data RegisterEasy · Verilog / SystemVerilog / VHDL Four-Sample Delay LineEasy · SystemVerilog DSP Valid PipelineEasy · SystemVerilog Streaming FIR Pipeline TopHard · SystemVerilog Streaming Byte Position CounterEasy · SystemVerilog EtherType ExtractorMedium · SystemVerilog IPv4 Protocol ExtractorMedium · SystemVerilog UDP Port ExtractorMedium · SystemVerilog Packet Statistics CountersEasy · SystemVerilog Streaming Ethernet/IPv4/UDP ParserHard · SystemVerilog Feed Word CounterEasy · SystemVerilog Market Message Header DecoderMedium · SystemVerilog Symbol FilterMedium · SystemVerilog Price / Quantity ExtractorMedium · SystemVerilog Message ClassifierEasy · SystemVerilog Feed Latency MeterMedium · SystemVerilog Low-Latency Market Data ParserHard · SystemVerilog SPI Clock DividerEasy · SystemVerilog SPI SCLK GeneratorMedium · SystemVerilog SPI Sample / Shift Edge ClassifierMedium · SystemVerilog SPI MOSI Shift RegisterMedium · SystemVerilog SPI MISO Receive RegisterMedium · SystemVerilog SPI Chip-Select ControllerEasy · SystemVerilog SPI Transfer Bit CounterMedium · SystemVerilog Configurable SPI MasterHard · SystemVerilog

Accelerators

Study the hardware accelerator design guide

Signed INT8 Multiply-AccumulateEasy · Verilog / SystemVerilog Four-Lane INT8 Dot ProductMedium · Verilog / SystemVerilog Eight-Lane Reduction AdderMedium · Verilog / SystemVerilog ReLU with 8-bit SaturationMedium · Verilog / SystemVerilog Systolic Array Processing ElementHard · Verilog / SystemVerilog Valid-Tagged Pipelined MultiplierHard · Verilog / SystemVerilog 32-bit Population CountMedium · Verilog / SystemVerilog Four-Lane Signed Vector MaximumMedium · Verilog / SystemVerilog Q1.7 Fixed-Point MultiplierHard · Verilog / SystemVerilog Valid-Ready Streaming AccumulatorHard · Verilog / SystemVerilog 2x2 Matrix Multiply DatapathHard · Verilog / SystemVerilog Three-Tap INT8 ConvolutionMedium · Verilog / SystemVerilog Signed Fixed-Point MACMedium · Verilog / SystemVerilog Four-Tap FIR DatapathMedium · Verilog / SystemVerilog Signed Saturation StageHard · Verilog / SystemVerilog Matrix MAC Processing ElementMedium · Verilog / SystemVerilog Two-Element Dot ProductEasy · Verilog / SystemVerilog 2x2 Input Tile RegistersMedium · Verilog / SystemVerilog Matrix Compute ControllerMedium · Verilog / SystemVerilog Matrix Result BufferMedium · Verilog / SystemVerilog 2x2 Matrix-Multiply AcceleratorHard · Verilog / SystemVerilog Three-Row Line BufferMedium · Verilog / SystemVerilog 3x3 Sliding WindowMedium · Verilog / SystemVerilog Nine-Tap Convolution MACHard · Verilog / SystemVerilog Convolution Valid PipelineEasy · Verilog / SystemVerilog 8-bit Output ClampMedium · Verilog / SystemVerilog Streaming 3x3 Convolution AcceleratorHard · Verilog / SystemVerilog SIMD Lane ALUMedium · Verilog / SystemVerilog Four-Lane SIMD DatapathMedium · Verilog / SystemVerilog Vector Mask MergeEasy · Verilog / SystemVerilog Vector Reduction UnitMedium · Verilog / SystemVerilog Four-Lane SIMD Execution UnitHard · Verilog / SystemVerilog Memory-Copy DMA EngineHard · Verilog / SystemVerilog