AXI-Lite UVM Monitor
Observe completed bus activity without driving the DUT.
Task
Create a passive monitor with an analysis port. Reconstruct write and read transactions only when the corresponding ready/valid handshakes complete, then publish them.
Examples
- AW/W completion forms a write transaction.
- AR/R completion forms a read transaction.
Constraints
- Use `uvm_analysis_port #(axi_lite_item)`.
- Sample through the monitor clocking block.
- Call `ap.write(tr)` for observed transactions.
What this problem is testing
UVM interview problems test transaction flow, ownership, phasing, TLM connections, checking strategy, and whether components remain reusable and debuggable.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Trace one item from sequence creation through driver activity, monitor observation, and scoreboard checking.
- Inject a mismatch or protocol error to confirm the environment can fail for the correct reason.
- Check that handshakes and analysis connections cannot silently drop transactions.
- Run multiple transactions to exercise queues, ordering, and end-of-test behavior.
Common mistakes
- Putting checking logic in the driver.
- Dropping or duplicating items around sequencer-driver or analysis-port handshakes.
- Ending the test before outstanding transactions are checked.
- Reporting mismatches without enough diagnostic context.
Interview follow-up questions
- Which component should own the reference-model comparison?
- How would you debug a transaction that was driven but never reached the scoreboard?
Concepts to review
UVM, monitor, analysis port
Open AXI-Lite UVM Monitor in the HDLForge interactive editor.
Related problems
- Build a UVM Driver — Medium
- Reference Model Scoreboard — Hard
- Monitor-Only Interface Modport — Easy
- UVM Sequence Item — Medium
- UVM Sequence Body — Medium
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