Build a UVM Driver
Implement the core run phase of a UVM driver for a simple transaction.
Task
Get sequence items, drive their fields onto a virtual interface, and signal completion.
Examples
- get_next_item(req) → drive DUT → item_done()
Constraints
- Use the UVM sequencer-driver handshake.
- Do not drop transactions.
What this problem is testing
UVM interview problems test transaction flow, ownership, phasing, TLM connections, checking strategy, and whether components remain reusable and debuggable.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Trace one item from sequence creation through driver activity, monitor observation, and scoreboard checking.
- Inject a mismatch or protocol error to confirm the environment can fail for the correct reason.
- Check that handshakes and analysis connections cannot silently drop transactions.
- Run multiple transactions to exercise queues, ordering, and end-of-test behavior.
Common mistakes
- Putting checking logic in the driver.
- Dropping or duplicating items around sequencer-driver or analysis-port handshakes.
- Ending the test before outstanding transactions are checked.
- Reporting mismatches without enough diagnostic context.
Interview follow-up questions
- Which component should own the reference-model comparison?
- How would you debug a transaction that was driven but never reached the scoreboard?
Concepts to review
driver, sequence_item
Open Build a UVM Driver in the HDLForge interactive editor.
Related problems
- Reference Model Scoreboard — Hard
- Backpressure-Aware Stream Driver — Medium
- UVM Sequence Item — Medium
- UVM Sequence Body — Medium
- UVM Monitor Analysis Port — Medium
Explore the UVM Practice & Interview Preparation hub.