UVM Sequence Body
Generate a stream of randomized sequence items.
Task
Extend uvm_sequence#(bus_item), repeat 20 times, create an item, start_item, randomize, and finish_item.
Examples
- Implement the requested verification structure or behavior.
Constraints
- Use SystemVerilog.
- Keep the code focused on the requested verification concept.
What this problem is testing
UVM interview problems test transaction flow, ownership, phasing, TLM connections, checking strategy, and whether components remain reusable and debuggable.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Trace one item from sequence creation through driver activity, monitor observation, and scoreboard checking.
- Inject a mismatch or protocol error to confirm the environment can fail for the correct reason.
- Check that handshakes and analysis connections cannot silently drop transactions.
- Run multiple transactions to exercise queues, ordering, and end-of-test behavior.
Common mistakes
- Putting checking logic in the driver.
- Dropping or duplicating items around sequencer-driver or analysis-port handshakes.
- Ending the test before outstanding transactions are checked.
- Reporting mismatches without enough diagnostic context.
Interview follow-up questions
- Which component should own the reference-model comparison?
- How would you debug a transaction that was driven but never reached the scoreboard?
Concepts to review
uvm, sequence, randomization
Open UVM Sequence Body in the HDLForge interactive editor.
Related problems
- Build a UVM Driver — Medium
- Reference Model Scoreboard — Hard
- Constrain Address Range — Easy
- Weighted Random Distribution — Medium
- UVM Sequence Item — Medium
Explore the UVM Practice & Interview Preparation hub.