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UVM Practice & Interview Preparation

Build UVM verification skills with sequence items, drivers, monitors, scoreboards, config_db, factory overrides and objection handling.

What interviewers usually look for

UVM interview problems test transaction flow, ownership, phasing, TLM connections, checking strategy, and whether components remain reusable and debuggable.

How to practise this topic

  1. Trace one item from sequence creation through driver activity, monitor observation, and scoreboard checking.
  2. Inject a mismatch or protocol error to confirm the environment can fail for the correct reason.
  3. Check that handshakes and analysis connections cannot silently drop transactions.

Practice problems

Build a UVM Driver
Medium · driver · sequence_item
Implement the core run phase of a UVM driver for a simple transaction.Reference Model Scoreboard
Hard · scoreboard · analysis · verification
Create a scoreboard that compares observed DUT output against a reference model.UVM Sequence Item
Medium · uvm · sequence-item · transaction
Define and register a simple randomized UVM transaction.UVM Sequence Body
Medium · uvm · sequence · randomization
Generate a stream of randomized sequence items.UVM Monitor Analysis Port
Medium · uvm · monitor · analysis-port
Publish observed transactions from a passive UVM monitor.UVM Agent Build and Connect
Hard · uvm · agent · sequencer · driver
Assemble a reusable active UVM agent.UVM Config DB Virtual Interface
Medium · uvm · config-db · virtual-interface
Retrieve a virtual interface from uvm_config_db.UVM Test Objections
Easy · uvm · objection · run-phase
Control UVM test lifetime with phase objections.AXI-Lite Verification Interface
Medium · UVM · AXI4-Lite · interface
Define the signal-level contract shared by the AXI-Lite DUT and UVM components.AXI-Lite Sequence Item
Medium · UVM · sequence item · randomization
Represent reads and writes as reusable randomized transactions.AXI-Lite UVM Driver
Hard · UVM · driver · ready-valid
Translate sequence items into protocol-correct AXI-Lite pin activity.AXI-Lite UVM Monitor
Hard · UVM · monitor · analysis port
Observe completed bus activity without driving the DUT.AXI-Lite Reference Scoreboard
Hard · UVM · scoreboard · reference model
Check reads against a compact reference register model updated by observed writes.AXI-Lite Functional Coverage
Medium · coverage · AXI4-Lite · cross coverage
Measure whether verification exercised operation types, address regions, byte strobes and responses.RISC-V Instruction Transaction
Medium · RISC-V · UVM · transaction
Represent an architectural instruction and its expected retirement information as a reusable verification transaction.Constrained RV32I Instruction Sequence
Hard · RISC-V · constrained random · UVM
Generate legal randomized RV32I arithmetic instructions for processor regression.AXI Crossbar Sequence Item
Medium · UVM · AXI · transaction
Represent one AXI-Lite write request including source master and target address.Constrained Crossbar Traffic Sequence
Hard · UVM · constrained random · AXI
Generate mapped and unmapped AXI-Lite write traffic from both masters.AXI Crossbar Monitor
Medium · UVM · monitor · AXI
Observe accepted AXI-Lite write transactions and publish them for checking.Crossbar Contention Sequence
Hard · UVM · arbitration · contention
Create sustained contention so both masters repeatedly target the same slave.

How to use this topic

Start with easier problems, implement or reason through the task without looking at a solution, then revisit medium and hard problems. Use the HDLForge roadmap to combine this topic with adjacent skills.

Follow the HDLForge roadmap or browse the complete problem set.

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