AXI-Lite Verification Interface
Define the signal-level contract shared by the AXI-Lite DUT and UVM components.
Task
Create an AXI-Lite SystemVerilog interface with AW, W, B, AR and R channel signals plus separate driver and monitor clocking blocks.
Examples
- Driver clocking block drives request/ready signals.
- Monitor clocking block samples all five AXI-Lite channels.
Constraints
- Use a single `clk` input.
- Declare AW/W/B/AR/R channel signals.
- Provide `drv_cb` and `mon_cb` clocking blocks.
What this problem is testing
UVM interview problems test transaction flow, ownership, phasing, TLM connections, checking strategy, and whether components remain reusable and debuggable.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Trace one item from sequence creation through driver activity, monitor observation, and scoreboard checking.
- Inject a mismatch or protocol error to confirm the environment can fail for the correct reason.
- Check that handshakes and analysis connections cannot silently drop transactions.
- Run multiple transactions to exercise queues, ordering, and end-of-test behavior.
Common mistakes
- Putting checking logic in the driver.
- Dropping or duplicating items around sequencer-driver or analysis-port handshakes.
- Ending the test before outstanding transactions are checked.
- Reporting mismatches without enough diagnostic context.
Interview follow-up questions
- Which component should own the reference-model comparison?
- How would you debug a transaction that was driven but never reached the scoreboard?
Concepts to review
UVM, AXI4-Lite, interface
Open AXI-Lite Verification Interface in the HDLForge interactive editor.
Related problems
- SystemVerilog Interface — Medium
- Build a UVM Driver — Medium
- Reference Model Scoreboard — Hard
- Interface Modports — Medium
- Interface Clocking Block — Medium
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