UVM · Medium · SystemVerilog

AXI-Lite Sequence Item

Represent reads and writes as reusable randomized transactions.

Task

Create a `uvm_sequence_item` containing operation type, address, write data, strobes, read data and response fields. Register every field with UVM automation macros.

Examples

• A write transaction carries address, data and byte strobes.
• A read transaction carries an address and later receives read data/response.

Constraints

• Address and write payload should be randomizable.
• Use `uvm_object_utils_begin/end`.
• Include response data for scoreboard/monitor use.

What this problem is testing

UVM interview problems test transaction flow, ownership, phasing, TLM connections, checking strategy, and whether components remain reusable and debuggable.

Verification plan

• Trace one item from sequence creation through driver activity, monitor observation, and scoreboard checking.
• Inject a mismatch or protocol error to confirm the environment can fail for the correct reason.
• Check that handshakes and analysis connections cannot silently drop transactions.
• Run multiple transactions to exercise queues, ordering, and end-of-test behavior.

Common mistakes

• Putting checking logic in the driver.
• Dropping or duplicating items around sequencer-driver or analysis-port handshakes.
• Ending the test before outstanding transactions are checked.
• Reporting mismatches without enough diagnostic context.

Interview follow-up questions

• Which component should own the reference-model comparison?
• How would you debug a transaction that was driven but never reached the scoreboard?

Concepts to review

UVM, sequence item, randomization

Open AXI-Lite Sequence Item in the HDLForge interactive editor.

Related problems

• Build a UVM Driver — Medium
• Reference Model Scoreboard — Hard
• Constrain Address Range — Easy
• Weighted Random Distribution — Medium
• UVM Sequence Item — Medium

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