RISC-V Instruction Transaction
Represent an architectural instruction and its expected retirement information as a reusable verification transaction.
Task
Create a `uvm_sequence_item` with randomized instruction word and PC plus observed rd/writeback fields. Register fields with UVM macros.
Examples
- Complete the required behavior and preserve it under the stated control conditions.
Constraints
- Use synthesizable SystemVerilog unless this is a verification-only stage.
What this problem is testing
UVM interview problems test transaction flow, ownership, phasing, TLM connections, checking strategy, and whether components remain reusable and debuggable.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Trace one item from sequence creation through driver activity, monitor observation, and scoreboard checking.
- Inject a mismatch or protocol error to confirm the environment can fail for the correct reason.
- Check that handshakes and analysis connections cannot silently drop transactions.
- Run multiple transactions to exercise queues, ordering, and end-of-test behavior.
Common mistakes
- Putting checking logic in the driver.
- Dropping or duplicating items around sequencer-driver or analysis-port handshakes.
- Ending the test before outstanding transactions are checked.
- Reporting mismatches without enough diagnostic context.
Interview follow-up questions
- Which component should own the reference-model comparison?
- How would you debug a transaction that was driven but never reached the scoreboard?
Concepts to review
RISC-V, UVM, transaction
Open RISC-V Instruction Transaction in the HDLForge interactive editor.
Related problems
- Build a UVM Driver — Medium
- Reference Model Scoreboard — Hard
- UVM Sequence Item — Medium
- UVM Sequence Body — Medium
- UVM Monitor Analysis Port — Medium
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