RTL Design · Hard · SystemVerilog

Direct-Mapped Cache Controller

Integrate address decode, hit detection and miss handling into a compact direct-mapped cache controller.

Task

Accept a request, return data immediately on hits, mark writes dirty, and raise miss_start on misses. Hold busy while a miss transaction is outstanding.

Examples

• Complete the required behavior and preserve it under the stated control conditions.

Constraints

• Use synthesizable SystemVerilog unless this is a verification-only stage.

What this problem is testing

A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.

Verification plan

• Check reset or initialization before normal operation.
• Exercise the nominal sequence cycle by cycle.
• Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
• Prove the design holds state when an enable or qualifying condition is absent.

Edge cases worth testing

• First and last byte within a line.
• Two addresses that map to the same set.

Common mistakes

• Incomplete combinational assignments that infer a latch.
• Blocking/non-blocking assignments that do not match combinational versus sequential intent.
• Parameter-width and boundary errors.
• Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.

Interview follow-up questions

• How would you parameterize this design without introducing width or boundary bugs?
• What changes if reset timing or polarity changes?

Concepts to review

cache, integration, memory controller

Open Direct-Mapped Cache Controller in the HDLForge interactive editor.

Related problems

• 2:1 Multiplexer — Easy
• Parameterized Counter — Easy
• Priority Encoder — Medium
• Synchronous FIFO — Hard
• Shift Register — Easy

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