RTL Design Practice & Interview Preparation
Practice synthesizable RTL design with focused exercises covering combinational logic, sequential logic, counters, FIFOs, arbiters, register files and timing-aware design.
What interviewers usually look for
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
How to practise this topic
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
Practice problems
2:1 Multiplexer
Design a synthesizable 2:1 multiplexer.Parameterized Counter
Build a parameterized synchronous up-counter with reset.Priority Encoder
Design an 8-to-3 priority encoder where bit 7 has the highest priority.Synchronous FIFO
Implement a synchronous parameterized FIFO with ready/valid-style enqueue and dequeue controls.Shift Register
Build a parameterized register that stores multiple bits and can shift its contents by one position on each clock edge.Rising Edge Detector
Generate a one-cycle pulse whenever an input signal transitions from 0 to 1.4-Request Priority Arbiter
A priority arbiter chooses one winner when multiple devices request access to a shared resource at the same time.Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.8-bit LFSR
Implement an 8-bit linear-feedback shift register for pseudo-random sequence generation.Programmable Clock Divider
Create a programmable divide-by-N toggle output.Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.Elastic Pipeline Register
Implement a single-stage pipeline register with an aligned valid bit.Asynchronous-Assert Reset Synchronizer
Create a two-flop reset synchronizer with asynchronous assertion and synchronous deassertion.Binary to Gray Counter
Build a parameterized binary counter and expose its Gray-code representation.Simple Dual-Port RAM
Infer a small synchronous-write, asynchronous-read dual-port memory.One-Hot Traffic-Light FSM
Implement a three-state one-hot finite-state machine.3-to-8 Decoder
Decode a 3-bit input into a one-hot 8-bit output.4-Way One-Hot Multiplexer
Select one of four 8-bit inputs using a one-hot select vector.16-bit Magnitude Comparator
Compare two unsigned 16-bit values.8-bit Barrel Shifter
Shift an 8-bit word left or right by 0-7 positions in one combinational stage.Leading-Zero Counter
Count the number of leading zeros in an 8-bit value.8-bit Population Count
Count how many bits are set in an 8-bit input.Four-Input Min/Max
Find the minimum and maximum of four unsigned 8-bit values.Even-Parity Generator
Generate the parity bit required to make an 8-bit word have even parity.Register with Clock Enable
Build an 8-bit register that updates only when enable is high.Toggle Flip-Flop
Toggle an output bit whenever toggle_en is asserted.Sticky Status Flag
Latch an event until software explicitly clears it.Pulse Stretcher
Stretch a one-cycle input pulse into a four-cycle output pulse.4-Cycle Delay Line
Delay an 8-bit sample by exactly four clock cycles.Serial-to-Parallel Receiver
Collect eight serial bits into one parallel byte.1011 Sequence Detector
Detect the serial bit pattern 1011 with overlapping matches allowed.Request/Acknowledge Controller
Control a request/acknowledge transaction.Pedestrian Crossing FSM
Control traffic and pedestrian signals through WAIT, STOP and WALK phases.Timeout and Retry FSM
Retry a request after a timeout, up to three attempts.Packet Header Parser FSM
Parse a four-byte header followed by payload bytes.Four-Beat Burst Controller
Control a fixed four-beat streaming burst.Vending Machine FSM
Accept 5-unit and 10-unit coins for a 15-unit item.Start/Busy/Done Controller
Implement a standard operation-control shell with start, busy and one-cycle done.Counted Synchronous FIFO
Build an 8-entry synchronous FIFO with an occupancy count.FIFO Almost-Full / Almost-Empty Flags
Generate almost_full and almost_empty from an occupancy count for a 16-entry FIFO.First-Word Fall-Through Buffer
Implement a two-entry first-word fall-through queue.FIFO Overflow / Underflow Sticky Flags
Record illegal FIFO access attempts.Two-Entry Elastic Buffer
Build a two-entry ready/valid elastic queue.Packet FIFO Boundary Tracker
Track packet-end metadata alongside FIFO data.Circular Sample Buffer
Continuously retain the most recent eight samples.Single-Entry Bypass Buffer
Pass data combinationally when empty, but capture it if downstream stalls.RISC-V Program Counter
Build the 32-bit program-counter register used by the guided RISC-V CPU project.RISC-V Instruction Decoder
Slice the fixed RV32I instruction fields used by the rest of the CPU datapath.RISC-V Register File
Create the 32 × 32-bit register file with two read ports, one write port and the architectural x0 rule.RISC-V Immediate Generator
Reassemble and sign-extend RV32I immediate fields for the CPU datapath.RISC-V ALU
Implement the arithmetic and logic unit used by the guided RV32I core.RISC-V Branch Control
Add the PC-relative target calculation and conditional branch decision logic.RISC-V Load/Store Control
Decode memory operations into read, write and register-writeback control signals.Integrate the 32-bit RISC-V Core
Bring the guided CPU blocks together into one single-cycle RV32I top-level datapath.UART Baud Tick Generator
Create the timing pulse that advances the UART transmitter and receiver.UART TX Frame Shifter
Build the shift register that serializes a UART frame.UART Transmit Controller
Control when a byte is loaded, shifted, and reported complete.UART RX Start-Bit Detector
Detect the beginning of an incoming UART frame.UART RX Data Shifter
Collect eight sampled serial data bits into a byte.UART Receive Controller
Coordinate start-bit detection, data sampling, and byte completion.Integrate the UART Controller
Combine the UART transmitter and receiver into one reusable controller.AXI-Lite Register Bank
Create the memory-mapped state that the AXI-Lite slave will expose.AXI-Lite AW Channel Capture
Accept the write address independently from write data.AXI-Lite W Channel Capture
Accept write data independently from the write address.AXI-Lite Write Commit
Pair independently captured AW and W payloads and commit one write.AXI-Lite B Response Channel
Return one write response and hold it until the master accepts it.AXI-Lite AR Channel Capture
Accept one AXI-Lite read address and preserve it while the read response is prepared.AXI-Lite R Response Channel
Return read data and keep it stable while the master applies backpressure.Integrate the AXI4-Lite Slave
Combine the independent AXI-Lite channels into a complete register-mapped slave.Async FIFO Dual-Port Memory
Create storage that can be written and read from different clock domains.Async FIFO Binary Pointers
Track independent write and read positions, including the wrap bit used by full detection.Binary-to-Gray Pointer Conversion
Convert a binary pointer to Gray code so only one bit changes per increment.Synchronize Gray Pointers
Move a Gray-coded pointer safely into the opposite clock domain.Async FIFO Empty Detection
Determine when the read pointer has caught up with the synchronized write pointer.Async FIFO Full Detection
Detect the wraparound relationship that means the write pointer is one complete buffer ahead of the read pointer.Per-Domain Reset Synchronizer
Release reset safely inside each asynchronous clock domain.Integrate the Asynchronous FIFO
Combine memory, pointers, Gray conversion, synchronization, and status detection into a complete dual-clock FIFO.IF/ID Pipeline Register
Create the first stage boundary that preserves fetched PC and instruction.ID/EX Pipeline Register
Carry decoded operands and control signals into the execute stage.EX Forwarding Unit
Resolve common RAW dependencies without stalling when the producer value is already available.Load-Use Hazard Detector
Detect the dependency that forwarding cannot resolve in time: an instruction immediately consuming a load result.Branch Redirect and Flush
Redirect fetch and invalidate younger work after a taken branch.Writeback Result Select
Select the value returned to the architectural register file.Pipeline Hazard Control Integration
Combine stall and redirect decisions into coherent controls for the PC and stage registers.Cache Address Decode
Split a 32-bit byte address into tag, index and word offset fields for a small direct-mapped cache.Cache Hit Detection
Determine whether the selected direct-mapped cache line contains the requested address.Cache Line Store
Store tag, valid, dirty and four 32-bit words for each direct-mapped cache line.Cache Miss / Refill FSM
Sequence lookup, optional writeback and four-word line refill after a cache miss.Four-Beat Refill Counter
Track the four words transferred while refilling a cache line.Direct-Mapped Cache Controller
Integrate address decode, hit detection and miss handling into a compact direct-mapped cache controller.2-bit Saturating Counter
Implement the classic four-state branch-direction predictor.Branch History Table
Scale the two-bit predictor into a small PC-indexed Branch History Table.Branch Target Buffer
Cache branch targets so a taken prediction can redirect fetch immediately.Predicted Next-PC Select
Use direction and target predictions to select the speculative next fetch address.Misprediction Detection
Detect when speculative fetch disagrees with the resolved branch outcome or target.Branch Predictor Top
Combine direction prediction, target lookup and resolved-branch update behavior.SoC Address Decoder
Decode the processor address into ROM, RAM, UART, GPIO and timer chip-selects.Boot ROM
Provide a tiny combinational boot ROM addressed by word index.Word-Addressed Data RAM
Implement a 1 KB data RAM with byte write enables.Memory-Mapped GPIO
Create a memory-mapped GPIO peripheral with an output register and sampled input register.Machine Timer Peripheral
Implement a free-running 32-bit timer and programmable compare register.Interrupt Controller
Combine UART, GPIO and timer interrupt requests into one CPU interrupt plus a cause code.Small RISC-V SoC Integration
Integrate memory-map decoding and response multiplexing for a small processor system.Vector Register File
Store eight architectural vector registers, each containing four 32-bit lanes.SIMD Execute Pipeline Register
Pipeline a 128-bit vector result and its validity bit.DMA Control Registers
Implement programmable source, destination and transfer-length registers.DMA Address Generator
Track source and destination word addresses during a transfer.DMA Read Channel
Issue one memory read request and hold it until accepted.DMA Write Channel
Buffer a read result and hold the write request until the destination accepts it.DMA Transfer Counter
Track remaining bytes and detect the final word transfer.DMA Transfer Controller
Sequence one read and one write for each copied word.AXI Crossbar Address Decoder
Decode a 32-bit request address to one of three AXI-Lite slaves.Two-Master Round-Robin Arbiter
Choose one of two requesting AXI masters fairly.AXI Request Router
Route one selected master's address and write data toward one selected slave.AXI Write Ownership Lock
Remember which master owns a write transaction until its B response completes.AXI Response Router
Route one slave write response back to the master that owns the transaction.AXI Decode Error Responder
Generate an AXI DECERR response for unmapped accesses without contacting a slave.2x3 AXI-Lite Crossbar Top
Integrate arbitration, address decode and transaction ownership for a two-master, three-slave AXI-Lite write crossbar.Peripheral Reset Controller
Generate a clean peripheral reset release from an asynchronous active-low external reset.APB Peripheral Decoder
Decode one APB request to GPIO, timer or UART.APB Read/Response Multiplexer
Combine three APB slave responses onto one upstream interface.APB GPIO Peripheral
Implement a 16-bit GPIO output register and sampled input register behind APB.APB Timer Peripheral
Implement a programmable timer with compare interrupt behind APB.UART Register Block
Expose transmit data and status as memory-mapped UART registers.APB Peripheral Subsystem Top
Integrate APB decode and interrupt aggregation for GPIO, timer and UART peripherals.I²C START / STOP Detector
Detect I²C START and STOP conditions from synchronized SDA/SCL samples.I²C Address Matcher
Decode the first I²C byte into a 7-bit address and R/W bit.I²C Byte Receiver
Receive one I²C byte by sampling SDA on SCL rising-edge pulses.I²C ACK / NACK Driver
Drive ACK using open-drain SDA behavior.I²C Byte Transmitter
Transmit one byte MSB-first using open-drain SDA.I²C Register Pointer
Maintain the internal register address used by an I²C register peripheral.I²C Clock-Stretch Control
Model clock stretching as an open-drain SCL request.Memory-Mapped I²C Register Slave
Integrate a simplified I²C register peripheral with address matching, ACK generation, register writes and sequential register reads.
Design a synthesizable 2:1 multiplexer.Parameterized Counter
Build a parameterized synchronous up-counter with reset.Priority Encoder
Design an 8-to-3 priority encoder where bit 7 has the highest priority.Synchronous FIFO
Implement a synchronous parameterized FIFO with ready/valid-style enqueue and dequeue controls.Shift Register
Build a parameterized register that stores multiple bits and can shift its contents by one position on each clock edge.Rising Edge Detector
Generate a one-cycle pulse whenever an input signal transitions from 0 to 1.4-Request Priority Arbiter
A priority arbiter chooses one winner when multiple devices request access to a shared resource at the same time.Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.8-bit LFSR
Implement an 8-bit linear-feedback shift register for pseudo-random sequence generation.Programmable Clock Divider
Create a programmable divide-by-N toggle output.Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.Elastic Pipeline Register
Implement a single-stage pipeline register with an aligned valid bit.Asynchronous-Assert Reset Synchronizer
Create a two-flop reset synchronizer with asynchronous assertion and synchronous deassertion.Binary to Gray Counter
Build a parameterized binary counter and expose its Gray-code representation.Simple Dual-Port RAM
Infer a small synchronous-write, asynchronous-read dual-port memory.One-Hot Traffic-Light FSM
Implement a three-state one-hot finite-state machine.3-to-8 Decoder
Decode a 3-bit input into a one-hot 8-bit output.4-Way One-Hot Multiplexer
Select one of four 8-bit inputs using a one-hot select vector.16-bit Magnitude Comparator
Compare two unsigned 16-bit values.8-bit Barrel Shifter
Shift an 8-bit word left or right by 0-7 positions in one combinational stage.Leading-Zero Counter
Count the number of leading zeros in an 8-bit value.8-bit Population Count
Count how many bits are set in an 8-bit input.Four-Input Min/Max
Find the minimum and maximum of four unsigned 8-bit values.Even-Parity Generator
Generate the parity bit required to make an 8-bit word have even parity.Register with Clock Enable
Build an 8-bit register that updates only when enable is high.Toggle Flip-Flop
Toggle an output bit whenever toggle_en is asserted.Sticky Status Flag
Latch an event until software explicitly clears it.Pulse Stretcher
Stretch a one-cycle input pulse into a four-cycle output pulse.4-Cycle Delay Line
Delay an 8-bit sample by exactly four clock cycles.Serial-to-Parallel Receiver
Collect eight serial bits into one parallel byte.1011 Sequence Detector
Detect the serial bit pattern 1011 with overlapping matches allowed.Request/Acknowledge Controller
Control a request/acknowledge transaction.Pedestrian Crossing FSM
Control traffic and pedestrian signals through WAIT, STOP and WALK phases.Timeout and Retry FSM
Retry a request after a timeout, up to three attempts.Packet Header Parser FSM
Parse a four-byte header followed by payload bytes.Four-Beat Burst Controller
Control a fixed four-beat streaming burst.Vending Machine FSM
Accept 5-unit and 10-unit coins for a 15-unit item.Start/Busy/Done Controller
Implement a standard operation-control shell with start, busy and one-cycle done.Counted Synchronous FIFO
Build an 8-entry synchronous FIFO with an occupancy count.FIFO Almost-Full / Almost-Empty Flags
Generate almost_full and almost_empty from an occupancy count for a 16-entry FIFO.First-Word Fall-Through Buffer
Implement a two-entry first-word fall-through queue.FIFO Overflow / Underflow Sticky Flags
Record illegal FIFO access attempts.Two-Entry Elastic Buffer
Build a two-entry ready/valid elastic queue.Packet FIFO Boundary Tracker
Track packet-end metadata alongside FIFO data.Circular Sample Buffer
Continuously retain the most recent eight samples.Single-Entry Bypass Buffer
Pass data combinationally when empty, but capture it if downstream stalls.RISC-V Program Counter
Build the 32-bit program-counter register used by the guided RISC-V CPU project.RISC-V Instruction Decoder
Slice the fixed RV32I instruction fields used by the rest of the CPU datapath.RISC-V Register File
Create the 32 × 32-bit register file with two read ports, one write port and the architectural x0 rule.RISC-V Immediate Generator
Reassemble and sign-extend RV32I immediate fields for the CPU datapath.RISC-V ALU
Implement the arithmetic and logic unit used by the guided RV32I core.RISC-V Branch Control
Add the PC-relative target calculation and conditional branch decision logic.RISC-V Load/Store Control
Decode memory operations into read, write and register-writeback control signals.Integrate the 32-bit RISC-V Core
Bring the guided CPU blocks together into one single-cycle RV32I top-level datapath.UART Baud Tick Generator
Create the timing pulse that advances the UART transmitter and receiver.UART TX Frame Shifter
Build the shift register that serializes a UART frame.UART Transmit Controller
Control when a byte is loaded, shifted, and reported complete.UART RX Start-Bit Detector
Detect the beginning of an incoming UART frame.UART RX Data Shifter
Collect eight sampled serial data bits into a byte.UART Receive Controller
Coordinate start-bit detection, data sampling, and byte completion.Integrate the UART Controller
Combine the UART transmitter and receiver into one reusable controller.AXI-Lite Register Bank
Create the memory-mapped state that the AXI-Lite slave will expose.AXI-Lite AW Channel Capture
Accept the write address independently from write data.AXI-Lite W Channel Capture
Accept write data independently from the write address.AXI-Lite Write Commit
Pair independently captured AW and W payloads and commit one write.AXI-Lite B Response Channel
Return one write response and hold it until the master accepts it.AXI-Lite AR Channel Capture
Accept one AXI-Lite read address and preserve it while the read response is prepared.AXI-Lite R Response Channel
Return read data and keep it stable while the master applies backpressure.Integrate the AXI4-Lite Slave
Combine the independent AXI-Lite channels into a complete register-mapped slave.Async FIFO Dual-Port Memory
Create storage that can be written and read from different clock domains.Async FIFO Binary Pointers
Track independent write and read positions, including the wrap bit used by full detection.Binary-to-Gray Pointer Conversion
Convert a binary pointer to Gray code so only one bit changes per increment.Synchronize Gray Pointers
Move a Gray-coded pointer safely into the opposite clock domain.Async FIFO Empty Detection
Determine when the read pointer has caught up with the synchronized write pointer.Async FIFO Full Detection
Detect the wraparound relationship that means the write pointer is one complete buffer ahead of the read pointer.Per-Domain Reset Synchronizer
Release reset safely inside each asynchronous clock domain.Integrate the Asynchronous FIFO
Combine memory, pointers, Gray conversion, synchronization, and status detection into a complete dual-clock FIFO.IF/ID Pipeline Register
Create the first stage boundary that preserves fetched PC and instruction.ID/EX Pipeline Register
Carry decoded operands and control signals into the execute stage.EX Forwarding Unit
Resolve common RAW dependencies without stalling when the producer value is already available.Load-Use Hazard Detector
Detect the dependency that forwarding cannot resolve in time: an instruction immediately consuming a load result.Branch Redirect and Flush
Redirect fetch and invalidate younger work after a taken branch.Writeback Result Select
Select the value returned to the architectural register file.Pipeline Hazard Control Integration
Combine stall and redirect decisions into coherent controls for the PC and stage registers.Cache Address Decode
Split a 32-bit byte address into tag, index and word offset fields for a small direct-mapped cache.Cache Hit Detection
Determine whether the selected direct-mapped cache line contains the requested address.Cache Line Store
Store tag, valid, dirty and four 32-bit words for each direct-mapped cache line.Cache Miss / Refill FSM
Sequence lookup, optional writeback and four-word line refill after a cache miss.Four-Beat Refill Counter
Track the four words transferred while refilling a cache line.Direct-Mapped Cache Controller
Integrate address decode, hit detection and miss handling into a compact direct-mapped cache controller.2-bit Saturating Counter
Implement the classic four-state branch-direction predictor.Branch History Table
Scale the two-bit predictor into a small PC-indexed Branch History Table.Branch Target Buffer
Cache branch targets so a taken prediction can redirect fetch immediately.Predicted Next-PC Select
Use direction and target predictions to select the speculative next fetch address.Misprediction Detection
Detect when speculative fetch disagrees with the resolved branch outcome or target.Branch Predictor Top
Combine direction prediction, target lookup and resolved-branch update behavior.SoC Address Decoder
Decode the processor address into ROM, RAM, UART, GPIO and timer chip-selects.Boot ROM
Provide a tiny combinational boot ROM addressed by word index.Word-Addressed Data RAM
Implement a 1 KB data RAM with byte write enables.Memory-Mapped GPIO
Create a memory-mapped GPIO peripheral with an output register and sampled input register.Machine Timer Peripheral
Implement a free-running 32-bit timer and programmable compare register.Interrupt Controller
Combine UART, GPIO and timer interrupt requests into one CPU interrupt plus a cause code.Small RISC-V SoC Integration
Integrate memory-map decoding and response multiplexing for a small processor system.Vector Register File
Store eight architectural vector registers, each containing four 32-bit lanes.SIMD Execute Pipeline Register
Pipeline a 128-bit vector result and its validity bit.DMA Control Registers
Implement programmable source, destination and transfer-length registers.DMA Address Generator
Track source and destination word addresses during a transfer.DMA Read Channel
Issue one memory read request and hold it until accepted.DMA Write Channel
Buffer a read result and hold the write request until the destination accepts it.DMA Transfer Counter
Track remaining bytes and detect the final word transfer.DMA Transfer Controller
Sequence one read and one write for each copied word.AXI Crossbar Address Decoder
Decode a 32-bit request address to one of three AXI-Lite slaves.Two-Master Round-Robin Arbiter
Choose one of two requesting AXI masters fairly.AXI Request Router
Route one selected master's address and write data toward one selected slave.AXI Write Ownership Lock
Remember which master owns a write transaction until its B response completes.AXI Response Router
Route one slave write response back to the master that owns the transaction.AXI Decode Error Responder
Generate an AXI DECERR response for unmapped accesses without contacting a slave.2x3 AXI-Lite Crossbar Top
Integrate arbitration, address decode and transaction ownership for a two-master, three-slave AXI-Lite write crossbar.Peripheral Reset Controller
Generate a clean peripheral reset release from an asynchronous active-low external reset.APB Peripheral Decoder
Decode one APB request to GPIO, timer or UART.APB Read/Response Multiplexer
Combine three APB slave responses onto one upstream interface.APB GPIO Peripheral
Implement a 16-bit GPIO output register and sampled input register behind APB.APB Timer Peripheral
Implement a programmable timer with compare interrupt behind APB.UART Register Block
Expose transmit data and status as memory-mapped UART registers.APB Peripheral Subsystem Top
Integrate APB decode and interrupt aggregation for GPIO, timer and UART peripherals.I²C START / STOP Detector
Detect I²C START and STOP conditions from synchronized SDA/SCL samples.I²C Address Matcher
Decode the first I²C byte into a 7-bit address and R/W bit.I²C Byte Receiver
Receive one I²C byte by sampling SDA on SCL rising-edge pulses.I²C ACK / NACK Driver
Drive ACK using open-drain SDA behavior.I²C Byte Transmitter
Transmit one byte MSB-first using open-drain SDA.I²C Register Pointer
Maintain the internal register address used by an I²C register peripheral.I²C Clock-Stretch Control
Model clock stretching as an open-drain SCL request.Memory-Mapped I²C Register Slave
Integrate a simplified I²C register peripheral with address matching, ACK generation, register writes and sequential register reads.
How to use this topic
Start with easier problems, implement or reason through the task without looking at a solution, then revisit medium and hard problems. Use the HDLForge roadmap to combine this topic with adjacent skills.
Follow the HDLForge roadmap or browse the complete problem set.
Related implementation guides
- Ready/Valid Handshake RTL Guide — Design ready/valid RTL correctly with backpressure, payload stability, skid buffers, elastic pipelines and executable HDLForge practice problems.
- Verilog FIFO Design Guide — Learn synchronous FIFO RTL in Verilog: pointers, occupancy, full/empty logic, simultaneous read/write behavior and verification edge cases.