Integrate the 32-bit RISC-V Core
Bring the guided CPU blocks together into one single-cycle RV32I top-level datapath.
Task
Instantiate the PC, decoder, register file and ALU, then complete the next-PC, memory and writeback paths.
Examples
- imem_addr follows pc
- pc_next selects branch_target or pc+4
- load writeback selects dmem_rdata instead of alu_result
Constraints
- Instantiate rv32_pc, rv32_decode, rv32_regs and rv32_alu.
- Drive the instruction-memory address from pc.
- Drive data-memory address/data from the ALU and rs2 path.
- Select memory data for load writeback.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
Concepts to review
RISC-V, CPU, integration
Open Integrate the 32-bit RISC-V Core in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
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