RISC-V Load/Store Control
Decode memory operations into read, write and register-writeback control signals.
Task
Decode LOAD and STORE opcodes into mem_read, mem_write and rd_write. Default every control low to prevent accidental writes.
Examples
- LOAD 0000011 → mem_read=1 and rd_write=1
- STORE 0100011 → mem_write=1
Constraints
- Use safe defaults.
- LOAD writes a register; STORE does not.
- Keep control combinational.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
Concepts to review
RISC-V, load-store, control
Open RISC-V Load/Store Control in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
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