Shift Register
Build a parameterized register that stores multiple bits and can shift its contents by one position on each clock edge.
Task
Design a synchronous shift register with a configurable width. `dout` stores the register's current contents.
Examples
- Input: reset = 1 shift_en = X din = X dout = 8'b10110110 After rising edge: dout = 8'b00000000
- Input: reset = 0 shift_en = 1 din = 1 dout = 8'b00000000 After rising edge: dout = 8'b00000001
- Input: reset = 0 shift_en = 1 din = 0 dout = 8'b00000001 After rising edge: dout = 8'b00000010
Constraints
- WIDTH must control the number of stored bits.
- reset is synchronous and active high, so it is sampled on the rising edge of clk.
- When reset is high, reset takes priority over shift_en.
- When shift_en is high, shift toward the MSB: dout[0] receives din and every other bit receives the bit below it.
- When shift_en is low and reset is low, dout must hold its previous value.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
Concepts to review
sequential, shift-register
Open Shift Register in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Rising Edge Detector — Easy
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