RTL Design · Medium · Verilog, SystemVerilog, VHDL

Priority Encoder

Design an 8-to-3 priority encoder where bit 7 has the highest priority.

Task

Return the index of the highest set input bit and a valid flag.

Examples

Constraints

What this problem is testing

A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.

Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.

Verification plan

Common mistakes

Interview follow-up questions

Concepts to review

combinational, encoder

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