Per-Domain Reset Synchronizer
Release reset safely inside each asynchronous clock domain.
Task
Create an active-low reset synchronizer with asynchronous assertion and two-clock synchronous deassertion.
Examples
- arst_n=0 → srst_n becomes 0 immediately
- arst_n rises → srst_n becomes 1 after two clk edges
Constraints
- Use `negedge arst_n` for asynchronous assertion.
- Use two stages for deassertion.
- Apply one instance per clock domain.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Edge cases worth testing
- A transition close to the destination clock edge.
- A pulse shorter than a destination clock period.
- Reset asserted during active operation.
- The first cycle after reset is released.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
Concepts to review
CDC, reset, synchronizer
Open Per-Domain Reset Synchronizer in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
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