RTL Design · Hard · SystemVerilog

Async FIFO Full Detection

Detect the wraparound relationship that means the write pointer is one complete buffer ahead of the read pointer.

Task

Assert `full` when the next write Gray pointer equals the synchronized read Gray pointer with its top two bits inverted.

Examples

Constraints

What this problem is testing

A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.

Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.

Verification plan

Edge cases worth testing

Common mistakes

Interview follow-up questions

Concepts to review

FIFO, full, Gray-code

Open Async FIFO Full Detection in the HDLForge interactive editor.

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