Streaming RTL / protocols

Ready/Valid Handshake RTL Guide

Ready/valid is one of the most reusable hardware interface patterns. The transfer rule is tiny—data moves only when VALID and READY are both high—but robust RTL also needs clear ownership, stable stalled data and deliberate buffering so timing pressure does not create combinational loops or lost transfers.

Core design rules

• A transfer occurs only on a clock edge where valid && ready is true.
• The source owns VALID and payload; while stalled, both must remain stable until the transfer completes.
• READY can be used to apply backpressure, but combinational dependencies across multiple stages should be controlled carefully.
• A skid buffer is useful when READY arrives too late to stop one in-flight item without losing it.

Implementation path

• Write the fire condition first and use it consistently for state updates.
• Implement a one-entry source register before attempting a multi-stage streaming pipeline.
• Add an elastic register or skid buffer and verify full-throughput back-to-back transfers.
• Pipeline data and control together; a valid bit that is one cycle misaligned is a functional bug.

Verification checklist

• Exercise always-ready, always-stalled and bursty READY patterns.
• Send back-to-back valid data and prove there are no drops, duplicates or reordering.
• Check that data remains stable for every cycle of a stall.
• Assert transfer counts at the input and output of buffered pipelines.

Useful RTL / verification pattern

wire fire = valid && ready;
// If valid && !ready, hold valid and payload stable.

Practice with executable problems

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