Hardware design projects
Build portfolio projects that go beyond toy RTL. Each guide defines what to build, which skills it demonstrates, how to verify it and what evidence to keep for interviews.
Start interactively: Build a 32-bit RISC-V CPU Core is available as a guided HDLForge lab.
RTL / Digital Design
Build a 32-bit RISC-V CPU Core
A guided way to build processor RTL while learning how instructions move through a real datapath.Three-Stage Pipelined RISC-V Core
Strong evidence of RTL design, control-path reasoning and processor fundamentals.Parameterized Cache or Memory Controller
Shows stateful RTL beyond simple interview blocks and connects architecture to implementation.Branch Predictor
Demonstrates performance-oriented CPU microarchitecture beyond the basic pipeline.SIMD / Vector Execution Unit
Connects CPU/GPU architecture concepts to a concrete parallel execution datapath.CDC-Safe Asynchronous FIFO
Demonstrates practical clock-domain-crossing knowledge expected in many digital design roles.
A guided way to build processor RTL while learning how instructions move through a real datapath.Three-Stage Pipelined RISC-V Core
Strong evidence of RTL design, control-path reasoning and processor fundamentals.Parameterized Cache or Memory Controller
Shows stateful RTL beyond simple interview blocks and connects architecture to implementation.Branch Predictor
Demonstrates performance-oriented CPU microarchitecture beyond the basic pipeline.SIMD / Vector Execution Unit
Connects CPU/GPU architecture concepts to a concrete parallel execution datapath.CDC-Safe Asynchronous FIFO
Demonstrates practical clock-domain-crossing knowledge expected in many digital design roles.
Design Verification
UVM Verification Environment for an AXI4-Lite Peripheral
Shows that you can verify a realistic bus-connected block end to end.RISC-V Core Verification
Demonstrates processor verification, debug discipline and coverage-driven thinking.Formal Verification of RTL Interfaces
Demonstrates proof-oriented verification beyond simulation and coverage-driven UVM.Formal Verification of a Cache Controller
Shows formal reasoning on a stateful memory subsystem instead of isolated protocol properties.AXI Interconnect Verification Environment
Demonstrates subsystem-level verification where arbitration, routing and backpressure interact.APB Peripheral Verification Suite
A compact way to show verification fundamentals before moving to AXI or processor-level work.
Shows that you can verify a realistic bus-connected block end to end.RISC-V Core Verification
Demonstrates processor verification, debug discipline and coverage-driven thinking.Formal Verification of RTL Interfaces
Demonstrates proof-oriented verification beyond simulation and coverage-driven UVM.Formal Verification of a Cache Controller
Shows formal reasoning on a stateful memory subsystem instead of isolated protocol properties.AXI Interconnect Verification Environment
Demonstrates subsystem-level verification where arbitration, routing and backpressure interact.APB Peripheral Verification Suite
A compact way to show verification fundamentals before moving to AXI or processor-level work.
FPGA
FPGA Packet Parser and Statistics Engine
Shows high-throughput datapath design and implementation awareness.UART/SPI/I2C Multi-Protocol Controller
Demonstrates interface design, integration and practical FPGA bring-up skills.SPI Controller
Demonstrates a real board-level serial interface and precise edge-sensitive control logic.Hardware DSP Pipeline
Useful evidence for FPGA roles involving signal processing or accelerator datapaths.Matrix-Multiplication Accelerator
Shows how parallel arithmetic, buffering and flow control combine into a practical hardware accelerator.Convolution Accelerator
Shows how image-processing kernels map into high-throughput hardware datapaths.
Shows high-throughput datapath design and implementation awareness.UART/SPI/I2C Multi-Protocol Controller
Demonstrates interface design, integration and practical FPGA bring-up skills.SPI Controller
Demonstrates a real board-level serial interface and precise edge-sensitive control logic.Hardware DSP Pipeline
Useful evidence for FPGA roles involving signal processing or accelerator datapaths.Matrix-Multiplication Accelerator
Shows how parallel arithmetic, buffering and flow control combine into a practical hardware accelerator.Convolution Accelerator
Shows how image-processing kernels map into high-throughput hardware datapaths.
SoC / Embedded Hardware
Small RISC-V SoC
Shows that you can move from isolated RTL blocks to a complete programmable system.I²C Peripheral / Slave
Demonstrates peripheral-side protocol handling and the hardware/software boundary of a common embedded interface.AXI4 Interconnect / Crossbar
Demonstrates the control and protocol logic behind scalable SoC fabrics.SoC Peripheral Subsystem
Shows practical subsystem integration around the hardware/software boundary.RISC-V Firmware + Hardware Bring-Up
Demonstrates that you can bring up and debug the software-visible side of custom hardware.AXI-Lite to APB Bridge
A realistic SoC integration block that exercises protocol and control-path reasoning.DMA Engine with Register Interface
Demonstrates control/datapath partitioning and common SoC subsystem concepts.
Shows that you can move from isolated RTL blocks to a complete programmable system.I²C Peripheral / Slave
Demonstrates peripheral-side protocol handling and the hardware/software boundary of a common embedded interface.AXI4 Interconnect / Crossbar
Demonstrates the control and protocol logic behind scalable SoC fabrics.SoC Peripheral Subsystem
Shows practical subsystem integration around the hardware/software boundary.RISC-V Firmware + Hardware Bring-Up
Demonstrates that you can bring up and debug the software-visible side of custom hardware.AXI-Lite to APB Bridge
A realistic SoC integration block that exercises protocol and control-path reasoning.DMA Engine with Register Interface
Demonstrates control/datapath partitioning and common SoC subsystem concepts.
Low-Latency / HFT Hardware
Low-Latency Market Data Parser
Shows the design style used for deterministic, line-rate FPGA processing without claiming any specific firm uses the exact design.Order Book Update Datapath
Demonstrates translating algorithmic state updates into deterministic hardware.Timestamped Feed-to-Action Pipeline
Makes latency engineering measurable and gives you a strong artifact to discuss in FPGA/HFT interviews.
Shows the design style used for deterministic, line-rate FPGA processing without claiming any specific firm uses the exact design.Order Book Update Datapath
Demonstrates translating algorithmic state updates into deterministic hardware.Timestamped Feed-to-Action Pipeline
Makes latency engineering measurable and gives you a strong artifact to discuss in FPGA/HFT interviews.