Timestamped Feed-to-Action Pipeline
Create a synthetic feed handler, rule engine and output-action path, timestamping stages to measure total and per-stage latency.
Why build it: Makes latency engineering measurable and gives you a strong artifact to discuss in FPGA/HFT interviews.
Key skills
Implementation plan
- Define a cycle-level latency budget and throughput target before coding.
- Avoid unnecessary buffering on the critical path and make backpressure behavior explicit.
- Use a reference model plus timestamped self-checking stimulus.
- Report measured per-stage latency, timing margin and resource trade-offs.
Verification plan
- Create a self-checking reference for the expected behavior before optimizing the RTL.
- Test reset and initialization, nominal operation, boundary conditions and back-to-back activity.
- Inject stalls, invalid requests or other stress cases when the interface permits them.
- Keep regression results, waveforms and failure notes so the project demonstrates debugging as well as coding.
Suggested deliverables
- RTL
- latency histogram/table
- testbench
- critical-path discussion
Problems to practise first
What to discuss in an interview
- The architecture you chose and the alternatives you rejected.
- The hardest bug or corner case and how you found it.
- How you verified correctness beyond one successful waveform.
- Timing, area, latency, coverage or protocol trade-offs relevant to the project.