HDLForge learning library

Hardware Design Learning & Interview Guides

Use these topic hubs and interview guides to move from concepts into focused practice. Every guide links into relevant HDLForge problems, creating a clear path between learning and hands-on work.

Hardware Design Interview Guide
A broad preparation guide covering RTL, verification, architecture, protocols and FPGA topics.Hardware Design Interview Questions
Interview-style questions for digital hardware roles.RTL Interview Guide
RTL design concepts and interview preparation.Verilog Interview Guide
Verilog coding and synthesizable RTL interview preparation.SystemVerilog Interview Guide
SystemVerilog design and verification interview preparation.RTL Design Exercises
Focused RTL exercises for hands-on practice.SVA Examples
SystemVerilog Assertion examples and temporal-property practice.UVM Interview Guide
UVM components, transactions, scoreboards and verification methodology.FPGA Interview Guide
FPGA design, timing, CDC and implementation interview topics.Computer Architecture Interview Guide
Pipelines, caches, hazards, latency and architecture interview topics.CDC Interview Guide
Metastability, synchronizers, handshakes and asynchronous FIFOs.AXI Ready/Valid Interview Guide
Ready/valid handshakes, backpressure and AXI-Lite reasoning.FPGA Timing Constraints Guide
Setup, hold, clock constraints and timing exceptions.RTL Design Practice
Browse RTL Design practice problems and preparation material.SystemVerilog Practice
Browse SystemVerilog practice problems and preparation material.SVA Practice
Browse SVA practice problems and preparation material.UVM Practice
Browse UVM practice problems and preparation material.Computer Architecture Practice
Browse Computer Architecture practice problems and preparation material.Protocols Practice
Browse Protocols practice problems and preparation material.FPGA Practice
Browse FPGA practice problems and preparation material.Hardware Accelerator Design Practice
MACs, vector datapaths, quantization, systolic arrays and accelerator pipelines.

Practice what you learn

Browse the complete HDLForge problem library.

HDLForge implementation deep dives

Implementation deep dives

Focused guides that connect hardware concepts directly to executable RTL and verification practice.

AXI-Lite Verification Guide
Learn how to verify AXI-Lite RTL with independent channel handshakes, assertions, scoreboards, backpressure tests and executable HDLForge practice.Ready/Valid Handshake RTL Guide
Design ready/valid RTL correctly with backpressure, payload stability, skid buffers, elastic pipelines and executable HDLForge practice problems.Verilog FIFO Design Guide
Learn synchronous FIFO RTL in Verilog: pointers, occupancy, full/empty logic, simultaneous read/write behavior and verification edge cases.Asynchronous FIFO and CDC Guide
Understand asynchronous FIFO RTL, Gray-code pointers, synchronizers, reset release and CDC verification with HDLForge practice and project links.Systolic Array RTL Design Guide
Learn systolic-array RTL from multiply-accumulate processing elements to data forwarding, pipeline timing and matrix-multiply verification.Hardware Accelerator RTL Design Guide
Learn hardware accelerator RTL through MACs, reductions, fixed-point arithmetic, streaming pipelines, quantization and systolic compute structures.UVM Scoreboard Guide
Build a practical UVM scoreboard with monitor transactions, reference-model prediction, analysis connections, mismatch reporting and coverage-aware verification.SVA Handshake Assertions Guide
Write SystemVerilog Assertions for ready/valid and bus handshakes: VALID hold, payload stability, responses, reset disabling and backpressure.