AI accelerator / datapath design

Systolic Array RTL Design Guide

A systolic array turns a regular arithmetic kernel into a spatial pipeline. Each processing element performs local work—usually multiply-accumulate—while operands move predictably between neighbours. The main RTL challenge is keeping arithmetic, forwarding and cycle alignment consistent across the array.

Core design rules

• Start from a processing element with explicit signed widths, accumulator width and enable/reset behavior.
• Forward operands and update the accumulator on well-defined clock edges so wavefront timing is deterministic.
• Size accumulators from the maximum dot-product length and operand range rather than relying on implicit truncation.
• Array-level correctness depends on launch timing: rows and columns may need deliberate staggering before products meet at the intended PE.

Implementation path

• Verify one MAC, then one forwarding PE, before instantiating a 2-D array.
• Create a small 2x2 matrix-multiply schedule on paper and annotate the expected cycle at each PE.
• Add valid/enable propagation if the array must support bubbles or repeated tiles.
• Measure initiation interval separately from total latency; a pipelined array can have high latency and still sustain high throughput.

Verification checklist

• Test positive, negative, zero and extreme signed operands.
• Compare against a software/reference matrix multiplication for randomized vectors.
• Check every PE accumulator and forwarding signal cycle-by-cycle for at least one tiny matrix.
• Send consecutive tiles or vectors to expose stale-state and valid-alignment bugs.

Useful RTL / verification pattern

// Conceptual PE update
if (enable) begin
  a_out <= a_in;
  b_out <= b_in;
  acc   <= acc + a_in * b_in;
end

Practice with executable problems

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