Accelerators · Medium · Verilog, SystemVerilog, VHDL

Four-Lane INT8 Dot Product

Implement a four-lane signed INT8 dot-product datapath similar to a small neural-network vector unit.

Task

Compute a0*b0 + a1*b1 + a2*b2 + a3*b3 combinationally and return the signed result.

Examples

• [1,2,3,4] dot [5,6,7,8] = 70
• [-1,2,-3,4] dot [4,3,2,1] = 0

Constraints

• All operands are signed 8-bit values.
• Use a wide enough signed result to avoid overflow for any legal inputs.
• The output must be purely combinational.

Accelerator verification checklist

• Exercise zero, maximum positive and negative operands where signed data is used.
• Check exact bit growth and make overflow or saturation behavior intentional.
• Verify reset, enable, valid and pipeline alignment cycle by cycle.
• Send back-to-back data to confirm the advertised throughput.

Concepts to review

accelerator, dot-product, simd, int8

Open Four-Lane INT8 Dot Product in the HDLForge interactive editor.

Related problems

• Signed INT8 Multiply-Accumulate — Easy
• Eight-Lane Reduction Adder — Medium
• ReLU with 8-bit Saturation — Medium
• Systolic Array Processing Element — Hard
• Valid-Tagged Pipelined Multiplier — Hard