Accelerators · Hard · Verilog, SystemVerilog, VHDL

Valid-Tagged Pipelined Multiplier

Implement a one-cycle-latency signed multiplier with an aligned valid signal, a common accelerator pipeline building block.

Task

When in_valid is sampled high, capture the signed 16x16 product. Assert out_valid exactly one cycle later with the corresponding 32-bit product. Back-to-back valid inputs must be supported.

Examples

in_valid with 7*-3 -> out_valid next cycle with -21
two consecutive valid inputs -> two consecutive valid outputs

Constraints

Operands are signed 16-bit.
Product is signed 32-bit.
Reset synchronously clears out_valid.
The datapath must accept one input every cycle.

Accelerator verification checklist

Exercise zero, maximum positive and negative operands where signed data is used.
Check exact bit growth and make overflow or saturation behavior intentional.
Verify reset, enable, valid and pipeline alignment cycle by cycle.
Send back-to-back data to confirm the advertised throughput.

Concepts to review

accelerator, pipeline, multiplier, throughput

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