Accelerators · Medium · Verilog, SystemVerilog, VHDL

Eight-Lane Reduction Adder

Create a parallel reduction block that sums eight 16-bit lanes into one output.

Task

Produce the exact unsigned sum of x0 through x7 combinationally.

Examples

• all lanes 1 -> sum=8
• all lanes 16'hFFFF -> sum=524280

Constraints

• Inputs are unsigned 16-bit values.
• The output must not overflow for the maximum possible input vector.
• Use synthesizable combinational RTL.

Accelerator verification checklist

• Exercise zero, maximum positive and negative operands where signed data is used.
• Check exact bit growth and make overflow or saturation behavior intentional.
• Verify reset, enable, valid and pipeline alignment cycle by cycle.
• Send back-to-back data to confirm the advertised throughput.

Concepts to review

accelerator, reduction-tree, parallelism, datapath

Open Eight-Lane Reduction Adder in the HDLForge interactive editor.

Related problems

• Signed INT8 Multiply-Accumulate — Easy
• Four-Lane INT8 Dot Product — Medium
• ReLU with 8-bit Saturation — Medium
• Systolic Array Processing Element — Hard
• Valid-Tagged Pipelined Multiplier — Hard