Accelerators · Medium · Verilog, SystemVerilog, VHDL

ReLU with 8-bit Saturation

Implement a hardware activation stage that applies ReLU and saturates positive values to unsigned 8-bit range.

Task

For signed 16-bit x, output 0 when x is negative, x when 0<=x<=255, and 255 when x is greater than 255.

Examples

• x=-7 -> y=0
• x=42 -> y=42
• x=300 -> y=255

Constraints

• x is signed 16-bit.
• y is unsigned 8-bit.
• The design must be combinational and synthesizable.

Accelerator verification checklist

• Exercise zero, maximum positive and negative operands where signed data is used.
• Check exact bit growth and make overflow or saturation behavior intentional.
• Verify reset, enable, valid and pipeline alignment cycle by cycle.
• Send back-to-back data to confirm the advertised throughput.

Concepts to review

accelerator, relu, quantization, activation

Open ReLU with 8-bit Saturation in the HDLForge interactive editor.

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