Q1.7 Fixed-Point Multiplier
Multiply two signed Q1.7 fixed-point values and return a truncated Q1.7 result.
Task
Compute the signed 8x8 product, arithmetic-shift the Q2.14 result right by 7 fractional bits, and return the low signed 8-bit Q1.7 value.
Examples
- 0.5 (64) * 0.5 (64) -> 0.25 (32)
- -0.5 (-64) * 0.5 (64) -> -0.25 (-32)
Constraints
- Inputs and output are signed 8-bit two's-complement.
- No saturation is required.
- Combinational RTL.
Accelerator verification checklist
- Exercise zero, maximum positive and negative operands where signed data is used.
- Check exact bit growth and make overflow or saturation behavior intentional.
- Verify reset, enable, valid and pipeline alignment cycle by cycle.
- Send back-to-back data to confirm the advertised throughput.
Concepts to review
accelerator, fixed-point, multiplier, quantization
Open Q1.7 Fixed-Point Multiplier in the HDLForge interactive editor.
Related problems
- Signed INT8 Multiply-Accumulate — Easy
- Four-Lane INT8 Dot Product — Medium
- Eight-Lane Reduction Adder — Medium
- ReLU with 8-bit Saturation — Medium
- Systolic Array Processing Element — Hard