Hardware DSP Pipeline
Implement a FIR filter, moving-average engine or fixed-point MAC pipeline with streaming valid/ready control.
Why build it: Useful evidence for FPGA roles involving signal processing or accelerator datapaths.
Key skills
Implementation plan
- Design for a target clock and realistic FPGA resources rather than simulation alone.
- Plan clock/reset domains, external interfaces and timing constraints early.
- Verify functionality before implementation, then inspect utilization and timing reports.
- Measure throughput/latency and document hardware-specific issues such as CDC or BRAM inference.
Verification plan
- Create a self-checking reference for the expected behavior before optimizing the RTL.
- Test reset and initialization, nominal operation, boundary conditions and back-to-back activity.
- Inject stalls, invalid requests or other stress cases when the interface permits them.
- Keep regression results, waveforms and failure notes so the project demonstrates debugging as well as coding.
Suggested deliverables
- RTL
- Python/MATLAB reference
- waveforms
- timing/utilization comparison
Problems to practise first
What to discuss in an interview
- The architecture you chose and the alternatives you rejected.
- The hardest bug or corner case and how you found it.
- How you verified correctness beyond one successful waveform.
- Timing, area, latency, coverage or protocol trade-offs relevant to the project.