AMBA / design verification

AXI-Lite Verification Guide

AXI-Lite looks simple because transactions carry only one data beat, but verification still has to respect independent address, data and response channels. A good testbench proves channel ordering, backpressure behavior, data stability and one-response-per-transaction behavior instead of testing only the fastest path.

Core design rules

• Treat AW and W as independent channels. A legal slave must not assume they arrive in the same cycle.
• Keep BVALID asserted until BREADY completes the response handshake.
• Check payload stability whenever a VALID signal is held while READY is low.
• Separate protocol checking from data checking: assertions catch temporal violations while a scoreboard checks architectural results.

Implementation path

• Start with a single-register write slave and make address/data capture explicit.
• Add directed cases for AW-before-W, W-before-AW, same-cycle arrival and delayed BREADY.
• Add SVA for VALID hold/stability, legal reset behavior and response persistence.
• Use a monitor/scoreboard path to prove that each accepted write updates the expected register exactly once.

Verification checklist

• Randomize the relative timing of AWVALID, WVALID and BREADY.
• Hold the response channel stalled for several cycles and verify BVALID does not disappear.
• Reset during idle and around transactions, then confirm no stale response survives.
• Count accepted write transactions and responses; the counts should remain consistent.

Useful RTL / verification pattern

// Transfer on each independent channel
aw_fire = awvalid && awready;
w_fire  = wvalid  && wready;
b_fire  = bvalid  && bready;

Practice with executable problems

Turn it into a project