AXI-Lite Write Register Slave
Implement the write side of a single-register AXI-Lite slave.
Task
Accept AW and W channels independently, update a 32-bit register once both have handshaken, then issue one OKAY write response.
Examples
- AW may arrive before W
- W may arrive before AW
- BVALID remains asserted until BREADY
Constraints
- Single outstanding write.
- BRESP must be OKAY (2'b00).
- Synchronous active-high reset.
What this problem is testing
Protocol questions test cycle-accurate sequencing, framing, handshake rules, backpressure, data stability, and the independence of channels or phases.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Exercise the fastest legal transfer and a stalled or backpressured transfer.
- Check payload and control stability while a transfer is pending.
- Test transaction boundaries and back-to-back transfers.
- Exercise malformed or unexpected sequencing when the specification defines a response.
Edge cases worth testing
- VALID held while READY is low.
- READY asserted before VALID.
- Back-to-back transfers without an idle cycle.
Common mistakes
- Assuming handshake signals must occur in one fixed order.
- Changing payload while a stalled transaction is still valid.
- Off-by-one errors around beats, bits, or completion.
- Coupling channels that the protocol defines as independent.
Interview follow-up questions
- How does the design behave under the slowest legal peer timing?
- Which signals must remain stable while a transfer is pending?
Concepts to review
axi-lite, amba, handshake, register
Open AXI-Lite Write Register Slave in the HDLForge interactive editor.
Related problems
- Synchronous FIFO — Hard
- Valid Must Eventually Handshake — Medium
- UART Transmitter — Medium
- SPI Master — Hard
- Backpressure-Safe Ready/Valid Source — Medium
Explore the Digital Protocol Practice: UART, SPI, AXI, APB & I2C hub.