APB Register Peripheral
Build a minimal APB peripheral exposing one 32-bit read/write register.
Task
Complete APB accesses in the enable phase. Writes to address 0 update the register; reads from address 0 return it. PREADY may stay high and PSLVERR low.
Examples
- PSEL=1,PENABLE=1,PWRITE=1 writes PWDATA
- read address 0 returns stored value
Constraints
- 32-bit data.
- Synchronous active-high reset.
- PREADY is always 1.
- PSLVERR is always 0.
What this problem is testing
Protocol questions test cycle-accurate sequencing, framing, handshake rules, backpressure, data stability, and the independence of channels or phases.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Exercise the fastest legal transfer and a stalled or backpressured transfer.
- Check payload and control stability while a transfer is pending.
- Test transaction boundaries and back-to-back transfers.
- Exercise malformed or unexpected sequencing when the specification defines a response.
Common mistakes
- Assuming handshake signals must occur in one fixed order.
- Changing payload while a stalled transaction is still valid.
- Off-by-one errors around beats, bits, or completion.
- Coupling channels that the protocol defines as independent.
Interview follow-up questions
- How does the design behave under the slowest legal peer timing?
- Which signals must remain stable while a transfer is pending?
Concepts to review
apb, amba, register-file, bus
Open APB Register Peripheral in the HDLForge interactive editor.
Related problems
- Small Register File — Medium
- UART Transmitter — Medium
- SPI Master — Hard
- Backpressure-Safe Ready/Valid Source — Medium
- AXI-Lite Write Register Slave — Hard
Explore the Digital Protocol Practice: UART, SPI, AXI, APB & I2C hub.