SPI Master
Implement a basic SPI mode-0 master for byte transfers.
Task
Generate SCLK and MOSI and sample MISO on the appropriate clock edge.
Examples
- mode 0 → CPOL=0, CPHA=0
Constraints
- Idle SCLK is low.
- Transmit MSB first.
What this problem is testing
Protocol questions test cycle-accurate sequencing, framing, handshake rules, backpressure, data stability, and the independence of channels or phases.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Exercise the fastest legal transfer and a stalled or backpressured transfer.
- Check payload and control stability while a transfer is pending.
- Test transaction boundaries and back-to-back transfers.
- Exercise malformed or unexpected sequencing when the specification defines a response.
Edge cases worth testing
- First and last sampled bit.
- Chip-select boundaries and the configured sampling edge.
Common mistakes
- Assuming handshake signals must occur in one fixed order.
- Changing payload while a stalled transaction is still valid.
- Off-by-one errors around beats, bits, or completion.
- Coupling channels that the protocol defines as independent.
Interview follow-up questions
- How does the design behave under the slowest legal peer timing?
- Which signals must remain stable while a transfer is pending?
Concepts to review
spi, serial, fsm
Open SPI Master in the HDLForge interactive editor.
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Explore the Digital Protocol Practice: UART, SPI, AXI, APB & I2C hub.