UART Transmitter
Design an 8-N-1 UART transmitter.
Task
Transmit a start bit, eight data bits LSB-first, and a stop bit at a programmable baud tick.
Examples
- 0x41 → start, 0,1,0,0,0,0,1,0, stop
Constraints
- Idle line is high.
- Use a single synchronous clock.
What this problem is testing
Protocol questions test cycle-accurate sequencing, framing, handshake rules, backpressure, data stability, and the independence of channels or phases.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Exercise the fastest legal transfer and a stalled or backpressured transfer.
- Check payload and control stability while a transfer is pending.
- Test transaction boundaries and back-to-back transfers.
- Exercise malformed or unexpected sequencing when the specification defines a response.
Edge cases worth testing
- Back-to-back frames.
- Start/stop timing and LSB-first ordering.
Common mistakes
- Assuming handshake signals must occur in one fixed order.
- Changing payload while a stalled transaction is still valid.
- Off-by-one errors around beats, bits, or completion.
- Coupling channels that the protocol defines as independent.
Interview follow-up questions
- How does the design behave under the slowest legal peer timing?
- Which signals must remain stable while a transfer is pending?
Concepts to review
uart, serial, fsm
Open UART Transmitter in the HDLForge interactive editor.
Related problems
- SPI Master — Hard
- Traffic Light FSM — Easy
- One-Hot Traffic-Light FSM — Medium
- Backpressure-Safe Ready/Valid Source — Medium
- APB Register Peripheral — Hard
Explore the Digital Protocol Practice: UART, SPI, AXI, APB & I2C hub.