Protocols · Medium · Verilog, SystemVerilog, VHDL

Backpressure-Safe Ready/Valid Source

Implement a source register that obeys ready/valid protocol semantics.

Task

When load is asserted while the source can accept a new value, capture load_data and assert valid. Keep valid and data stable until ready completes the transfer.

Examples

• load data while idle -> valid=1
• valid=1 and ready=0 -> hold data
• valid=1 and ready=1 -> transfer completes

Constraints

• Single-entry source buffer.
• Synchronous active-high reset.
• No data changes while stalled.

What this problem is testing

Protocol questions test cycle-accurate sequencing, framing, handshake rules, backpressure, data stability, and the independence of channels or phases.

Verification plan

• Exercise the fastest legal transfer and a stalled or backpressured transfer.
• Check payload and control stability while a transfer is pending.
• Test transaction boundaries and back-to-back transfers.
• Exercise malformed or unexpected sequencing when the specification defines a response.

Edge cases worth testing

• VALID held while READY is low.
• READY asserted before VALID.
• Back-to-back transfers without an idle cycle.

Common mistakes

• Assuming handshake signals must occur in one fixed order.
• Changing payload while a stalled transaction is still valid.
• Off-by-one errors around beats, bits, or completion.
• Coupling channels that the protocol defines as independent.

Interview follow-up questions

• How does the design behave under the slowest legal peer timing?
• Which signals must remain stable while a transfer is pending?

Concepts to review

ready-valid, handshake, backpressure

Open Backpressure-Safe Ready/Valid Source in the HDLForge interactive editor.

Related problems

• Synchronous FIFO — Hard
• Valid Must Eventually Handshake — Medium
• UART Transmitter — Medium
• SPI Master — Hard
• Ready/Valid Skid Buffer — Hard

Explore the Digital Protocol Practice: UART, SPI, AXI, APB & I2C hub.

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