Traffic Light FSM
Design a finite-state machine controlling a simple traffic light sequence.
Task
Cycle through green, yellow and red states with configurable durations.
Examples
- GREEN → YELLOW → RED → GREEN
Constraints
- Use an enumerated state type.
- No latches in next-state logic.
What this problem is testing
FPGA problems test whether logically correct RTL will behave predictably in hardware, including clock-domain boundaries, reset release, noisy inputs, inferred resources, and timing.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Separate functional checks from implementation concerns such as CDC and timing.
- Test asynchronous or noisy inputs with realistic transitions when relevant.
- Confirm reset assertion and release do not create unintended pulses or state.
- Review whether the RTL infers the intended FPGA resource.
Common mistakes
- Treating an asynchronous input as synchronous.
- Using a simple synchronizer for a pulse or multi-bit bus when a different CDC structure is needed.
- Generating clocks in ordinary RTL when a clock enable would be safer.
- Ignoring implementation timing because behavioral simulation passes.
Interview follow-up questions
- What hardware-specific issue could make a simulation-only solution unreliable?
- What timing or CDC check would you review before sign-off?
Concepts to review
fsm, state-machine
Open Traffic Light FSM in the HDLForge interactive editor.
Related problems
- UART Transmitter — Medium
- SPI Master — Hard
- Button Debouncer — Easy
- One-Hot Traffic-Light FSM — Medium
- Parameterized PWM Generator — Easy
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