FPGA Design Practice & Interview Preparation
Practice FPGA-oriented design topics including debouncing, FSMs, CDC synchronizers, BRAM inference, timing constraints and reset strategy.
What interviewers usually look for
FPGA problems test whether logically correct RTL will behave predictably in hardware, including clock-domain boundaries, reset release, noisy inputs, inferred resources, and timing.
How to practise this topic
- Separate functional checks from implementation concerns such as CDC and timing.
- Test asynchronous or noisy inputs with realistic transitions when relevant.
- Confirm reset assertion and release do not create unintended pulses or state.
Practice problems
Button Debouncer
Create a synchronous button debouncer suitable for an FPGA.Traffic Light FSM
Design a finite-state machine controlling a simple traffic light sequence.Parameterized PWM Generator
Generate a PWM waveform from an unsigned duty-cycle input.Toggle-Based Pulse Synchronizer
Transfer a one-cycle pulse between unrelated clock domains using a toggle synchronizer.Clock-Enable Data Register
Model the FPGA-friendly alternative to fabric clock gating: a register controlled by clock enable.Four-Sample Delay Line
Store the current and previous input samples for a four-tap FIR.DSP Valid Pipeline
Keep control timing aligned with a multi-stage arithmetic datapath.Streaming FIR Pipeline Top
Combine sample storage, FIR arithmetic and registered output into a streaming block.Streaming Byte Position Counter
Track byte position within a packet without buffering the complete frame.EtherType Extractor
Extract the Ethernet EtherType field from the word carrying bytes 12-15.IPv4 Protocol Extractor
Capture the IPv4 protocol byte after an Ethernet IPv4 frame is identified.UDP Port Extractor
Extract source and destination ports from a simplified fixed-header IPv4/UDP packet.Packet Statistics Counters
Maintain simple line-rate counters for total IPv4 packets and UDP packets.Streaming Ethernet/IPv4/UDP Parser
Integrate a fixed-latency streaming packet parser without full-frame buffering.Feed Word Counter
Track 32-bit word position inside each market-data message.Market Message Header Decoder
Decode a compact first-word header into message type and sequence number.Symbol Filter
Discard messages that do not match a configured symbol ID.Price / Quantity Extractor
Capture normalized price and quantity from consecutive feed words.Message Classifier
Classify three feed message types into add, update and delete operations.Feed Latency Meter
Measure cycle latency from message start to normalized output.Low-Latency Market Data Parser
Integrate a simplified fixed-format feed parser that emits normalized add/update/delete messages.SPI Clock Divider
Generate a programmable SPI clock-enable tick from the system clock.SPI SCLK Generator
Generate SCLK with programmable idle polarity.SPI Sample / Shift Edge Classifier
Classify each SCLK transition as a sample edge or a shift edge using CPHA.SPI MOSI Shift Register
Serialize one configurable-width transmit word MSB-first.SPI MISO Receive Register
Capture one receive word MSB-first from MISO.SPI Chip-Select Controller
Control an active-low SPI chip-select around a transfer.SPI Transfer Bit Counter
Track how many sample edges have occurred in a configurable transfer.Configurable SPI Master
Integrate a configurable SPI master supporting all four CPOL/CPHA modes.
Create a synchronous button debouncer suitable for an FPGA.Traffic Light FSM
Design a finite-state machine controlling a simple traffic light sequence.Parameterized PWM Generator
Generate a PWM waveform from an unsigned duty-cycle input.Toggle-Based Pulse Synchronizer
Transfer a one-cycle pulse between unrelated clock domains using a toggle synchronizer.Clock-Enable Data Register
Model the FPGA-friendly alternative to fabric clock gating: a register controlled by clock enable.Four-Sample Delay Line
Store the current and previous input samples for a four-tap FIR.DSP Valid Pipeline
Keep control timing aligned with a multi-stage arithmetic datapath.Streaming FIR Pipeline Top
Combine sample storage, FIR arithmetic and registered output into a streaming block.Streaming Byte Position Counter
Track byte position within a packet without buffering the complete frame.EtherType Extractor
Extract the Ethernet EtherType field from the word carrying bytes 12-15.IPv4 Protocol Extractor
Capture the IPv4 protocol byte after an Ethernet IPv4 frame is identified.UDP Port Extractor
Extract source and destination ports from a simplified fixed-header IPv4/UDP packet.Packet Statistics Counters
Maintain simple line-rate counters for total IPv4 packets and UDP packets.Streaming Ethernet/IPv4/UDP Parser
Integrate a fixed-latency streaming packet parser without full-frame buffering.Feed Word Counter
Track 32-bit word position inside each market-data message.Market Message Header Decoder
Decode a compact first-word header into message type and sequence number.Symbol Filter
Discard messages that do not match a configured symbol ID.Price / Quantity Extractor
Capture normalized price and quantity from consecutive feed words.Message Classifier
Classify three feed message types into add, update and delete operations.Feed Latency Meter
Measure cycle latency from message start to normalized output.Low-Latency Market Data Parser
Integrate a simplified fixed-format feed parser that emits normalized add/update/delete messages.SPI Clock Divider
Generate a programmable SPI clock-enable tick from the system clock.SPI SCLK Generator
Generate SCLK with programmable idle polarity.SPI Sample / Shift Edge Classifier
Classify each SCLK transition as a sample edge or a shift edge using CPHA.SPI MOSI Shift Register
Serialize one configurable-width transmit word MSB-first.SPI MISO Receive Register
Capture one receive word MSB-first from MISO.SPI Chip-Select Controller
Control an active-low SPI chip-select around a transfer.SPI Transfer Bit Counter
Track how many sample edges have occurred in a configurable transfer.Configurable SPI Master
Integrate a configurable SPI master supporting all four CPOL/CPHA modes.
How to use this topic
Start with easier problems, implement or reason through the task without looking at a solution, then revisit medium and hard problems. Use the HDLForge roadmap to combine this topic with adjacent skills.
Follow the HDLForge roadmap or browse the complete problem set.
Related implementation guides
- Asynchronous FIFO and CDC Guide — Understand asynchronous FIFO RTL, Gray-code pointers, synchronizers, reset release and CDC verification with HDLForge practice and project links.
- Verilog FIFO Design Guide — Learn synchronous FIFO RTL in Verilog: pointers, occupancy, full/empty logic, simultaneous read/write behavior and verification edge cases.