Message Classifier
Classify three feed message types into add, update and delete operations.
Task
Map type 0x01 to add, 0x02 to update and 0x03 to delete. All other types produce no class.
Examples
- Implement the required behavior and preserve it under the stated control conditions.
Constraints
- Use synthesizable SystemVerilog unless this stage is verification-only.
What this problem is testing
FPGA problems test whether logically correct RTL will behave predictably in hardware, including clock-domain boundaries, reset release, noisy inputs, inferred resources, and timing.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Separate functional checks from implementation concerns such as CDC and timing.
- Test asynchronous or noisy inputs with realistic transitions when relevant.
- Confirm reset assertion and release do not create unintended pulses or state.
- Review whether the RTL infers the intended FPGA resource.
Common mistakes
- Treating an asynchronous input as synchronous.
- Using a simple synchronizer for a pulse or multi-bit bus when a different CDC structure is needed.
- Generating clocks in ordinary RTL when a clock enable would be safer.
- Ignoring implementation timing because behavioral simulation passes.
Interview follow-up questions
- What hardware-specific issue could make a simulation-only solution unreliable?
- What timing or CDC check would you review before sign-off?
Concepts to review
HFT, classification, combinational
Open Message Classifier in the HDLForge interactive editor.
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