4-Request Priority Arbiter
A priority arbiter chooses one winner when multiple devices request access to a shared resource at the same time.
Task
Design a combinational 4-request priority arbiter. The input req[3:0] represents four requesters. A bit value of 1 means that requester is asking for access. Drive grant[3:0] so that only the highest-priority active requester is granted. Requester 3 has the highest priority and requester 0 has the lowest.
Examples
- req = 4'b0101 bits 2 and 0 are requesting grant = 4'b0100 Requester 2 wins because it has higher priority than requester 0.
- req = 4'b1011 bits 3, 1 and 0 are requesting grant = 4'b1000 Requester 3 wins because it has the highest priority.
- req = 4'b0000 grant = 4'b0000 No request means no grant.
Constraints
- The design must be purely combinational; no clock is required.
- Priority order is req[3] > req[2] > req[1] > req[0].
- grant must be one-hot or zero: at most one grant bit may be 1.
- If req is 4'b0000, grant must be 4'b0000.
- If multiple request bits are 1, only the highest-priority requester may be granted.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Edge cases worth testing
- No requests, one request, and simultaneous requests.
- Priority behavior when the highest-priority requester changes.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
Concepts to review
combinational, arbiter, priority
Open 4-Request Priority Arbiter in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
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