Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.
Task
Write wdata to waddr on the rising edge when we is asserted. Reads must reflect selected registers combinationally.
Examples
- write addr=2, data=0x5A → read addr=2 gives 0x5A
- reset → all registers are zero
Constraints
- 4 registers, 8 bits each.
- Reset is synchronous and clears all registers.
- Do not add a clock to the read path.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Edge cases worth testing
- Read-after-write behavior.
- Address boundary values.
- Simultaneous accesses or collisions when the interface permits them.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
- What read-during-write behavior do you expect from the target memory?
Concepts to review
register-file, memory, sequential
Open Small Register File in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
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