8-bit LFSR
Implement an 8-bit linear-feedback shift register for pseudo-random sequence generation.
Task
Use feedback state[7]^state[5]^state[4]^state[3] and shift left when enabled.
Examples
- seed=0x01 → next=0x02
- seed=0x08 → next=0x11
Constraints
- Reset loads 8'h01.
- Hold state when enable is low.
- Never allow the state to become zero.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Edge cases worth testing
- Reset seed behavior.
- Protection against the all-zero lock-up state.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
Concepts to review
sequential, lfsr, pseudo-random
Open 8-bit LFSR in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
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