UDP Port Extractor
Extract source and destination ports from a simplified fixed-header IPv4/UDP packet.
Task
When protocol is 17 and byte_pos equals 34, capture source port from data[31:16] and destination port from data[15:0].
Examples
- Complete the required behavior and preserve it under the stated control conditions.
Constraints
- Use synthesizable SystemVerilog unless this is a verification-only stage.
What this problem is testing
FPGA problems test whether logically correct RTL will behave predictably in hardware, including clock-domain boundaries, reset release, noisy inputs, inferred resources, and timing.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Separate functional checks from implementation concerns such as CDC and timing.
- Test asynchronous or noisy inputs with realistic transitions when relevant.
- Confirm reset assertion and release do not create unintended pulses or state.
- Review whether the RTL infers the intended FPGA resource.
Common mistakes
- Treating an asynchronous input as synchronous.
- Using a simple synchronizer for a pulse or multi-bit bus when a different CDC structure is needed.
- Generating clocks in ordinary RTL when a clock enable would be safer.
- Ignoring implementation timing because behavioral simulation passes.
Interview follow-up questions
- What hardware-specific issue could make a simulation-only solution unreliable?
- What timing or CDC check would you review before sign-off?
Concepts to review
UDP, parser, ports
Open UDP Port Extractor in the HDLForge interactive editor.
Related problems
- Button Debouncer — Easy
- Traffic Light FSM — Easy
- Parameterized PWM Generator — Easy
- Toggle-Based Pulse Synchronizer — Hard
- Clock-Enable Data Register — Easy
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