FPGA · Hard · Verilog, SystemVerilog, VHDL

Toggle-Based Pulse Synchronizer

Transfer a one-cycle pulse between unrelated clock domains using a toggle synchronizer.

Task

Toggle a source-domain bit on each src_pulse, synchronize it through two destination flops, and generate one dst_pulse when the synchronized toggle changes.

Examples

Constraints

What this problem is testing

FPGA problems test whether logically correct RTL will behave predictably in hardware, including clock-domain boundaries, reset release, noisy inputs, inferred resources, and timing.

Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.

Verification plan

Edge cases worth testing

Common mistakes

Interview follow-up questions

Concepts to review

cdc, pulse, synchronizer, fpga

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