Clock-Enable Data Register
Model the FPGA-friendly alternative to fabric clock gating: a register controlled by clock enable.
Task
Capture d on each rising edge only when ce is high; otherwise hold q.
Examples
- ce=1 -> q captures d
- ce=0 -> q holds its previous value
Constraints
- Synchronous active-high reset.
- Parameterized width.
- Do not gate the clock.
What this problem is testing
FPGA problems test whether logically correct RTL will behave predictably in hardware, including clock-domain boundaries, reset release, noisy inputs, inferred resources, and timing.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Separate functional checks from implementation concerns such as CDC and timing.
- Test asynchronous or noisy inputs with realistic transitions when relevant.
- Confirm reset assertion and release do not create unintended pulses or state.
- Review whether the RTL infers the intended FPGA resource.
Common mistakes
- Treating an asynchronous input as synchronous.
- Using a simple synchronizer for a pulse or multi-bit bus when a different CDC structure is needed.
- Generating clocks in ordinary RTL when a clock enable would be safer.
- Ignoring implementation timing because behavioral simulation passes.
Interview follow-up questions
- What hardware-specific issue could make a simulation-only solution unreliable?
- What timing or CDC check would you review before sign-off?
Concepts to review
clock-enable, fpga, sequential
Open Clock-Enable Data Register in the HDLForge interactive editor.
Related problems
- Parameterized Counter — Easy
- Shift Register — Easy
- Rising Edge Detector — Easy
- Small Register File — Medium
- 8-bit LFSR — Medium
Explore the FPGA Design Practice & Interview Preparation hub.