Accelerators · Medium · Verilog, SystemVerilog, VHDL

32-bit Population Count

Build a combinational population-count unit that returns the number of set bits in a 32-bit word.

Task

Count all one bits in x and return a value from 0 to 32.

Examples

• x=0 -> count=0
• x=32'hFFFFFFFF -> count=32
• x=32'hF0F0F0F0 -> count=16

Constraints

• Combinational and synthesizable.
• Output width must represent 32.

Accelerator verification checklist

• Exercise zero, maximum positive and negative operands where signed data is used.
• Check exact bit growth and make overflow or saturation behavior intentional.
• Verify reset, enable, valid and pipeline alignment cycle by cycle.
• Send back-to-back data to confirm the advertised throughput.

Concepts to review

accelerator, popcount, reduction, bit-manipulation

Open 32-bit Population Count in the HDLForge interactive editor.

Related problems

• Signed INT8 Multiply-Accumulate — Easy
• Four-Lane INT8 Dot Product — Medium
• Eight-Lane Reduction Adder — Medium
• ReLU with 8-bit Saturation — Medium
• Systolic Array Processing Element — Hard