Streaming FIR Pipeline Top
Combine sample storage, FIR arithmetic and registered output into a streaming block.
Task
Create a four-tap FIR top that accepts `in_valid`, shifts samples, computes the weighted sum, registers the saturated result and asserts `out_valid` with the registered output.
Examples
- Each valid input advances the filter.
- Output validity is delayed to match the registered result.
Constraints
- Instantiate/use a four-sample history.
- Use four coefficients.
- Register output and valid together.
What this problem is testing
FPGA problems test whether logically correct RTL will behave predictably in hardware, including clock-domain boundaries, reset release, noisy inputs, inferred resources, and timing.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Separate functional checks from implementation concerns such as CDC and timing.
- Test asynchronous or noisy inputs with realistic transitions when relevant.
- Confirm reset assertion and release do not create unintended pulses or state.
- Review whether the RTL infers the intended FPGA resource.
Common mistakes
- Treating an asynchronous input as synchronous.
- Using a simple synchronizer for a pulse or multi-bit bus when a different CDC structure is needed.
- Generating clocks in ordinary RTL when a clock enable would be safer.
- Ignoring implementation timing because behavioral simulation passes.
Interview follow-up questions
- What hardware-specific issue could make a simulation-only solution unreliable?
- What timing or CDC check would you review before sign-off?
Concepts to review
DSP, streaming, integration
Open Streaming FIR Pipeline Top in the HDLForge interactive editor.
Related problems
- Button Debouncer — Easy
- Traffic Light FSM — Easy
- Parameterized PWM Generator — Easy
- Toggle-Based Pulse Synchronizer — Hard
- Clock-Enable Data Register — Easy
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