Signed Saturation Stage
Reduce a wide accumulator to a 16-bit output without wraparound on overflow.
Task
Saturate a signed 36-bit value to the signed 16-bit range [-32768, 32767].
Examples
- 40000 → 32767.
- -40000 → -32768.
- 1234 → 1234.
Constraints
- Combinational logic.
- Clamp positive and negative overflow.
- Preserve in-range values.
Accelerator verification checklist
- Exercise zero, maximum positive and negative operands where signed data is used.
- Check exact bit growth and make overflow or saturation behavior intentional.
- Verify reset, enable, valid and pipeline alignment cycle by cycle.
- Send back-to-back data to confirm the advertised throughput.
Concepts to review
DSP, fixed point, saturation
Open Signed Saturation Stage in the HDLForge interactive editor.
Related problems
- Signed INT8 Multiply-Accumulate — Easy
- Four-Lane INT8 Dot Product — Medium
- Eight-Lane Reduction Adder — Medium
- ReLU with 8-bit Saturation — Medium
- Systolic Array Processing Element — Hard