FPGA · Medium · SystemVerilog

SPI MOSI Shift Register

Serialize one configurable-width transmit word MSB-first.

Task

Load tx_data when load is high. On each shift_edge, shift left and present the current MSB on MOSI.

Examples

• Implement the required protocol behavior and preserve it across the stated timing/control conditions.

Constraints

• Use synthesizable SystemVerilog and synchronous state/control logic unless the task explicitly requires edge detection or open-drain behavior.

What this problem is testing

FPGA problems test whether logically correct RTL will behave predictably in hardware, including clock-domain boundaries, reset release, noisy inputs, inferred resources, and timing.

Verification plan

• Separate functional checks from implementation concerns such as CDC and timing.
• Test asynchronous or noisy inputs with realistic transitions when relevant.
• Confirm reset assertion and release do not create unintended pulses or state.
• Review whether the RTL infers the intended FPGA resource.

Edge cases worth testing

• First and last sampled bit.
• Chip-select boundaries and the configured sampling edge.

Common mistakes

• Treating an asynchronous input as synchronous.
• Using a simple synchronizer for a pulse or multi-bit bus when a different CDC structure is needed.
• Generating clocks in ordinary RTL when a clock enable would be safer.
• Ignoring implementation timing because behavioral simulation passes.

Interview follow-up questions

• What hardware-specific issue could make a simulation-only solution unreliable?
• What timing or CDC check would you review before sign-off?

Concepts to review

SPI, MOSI, shift register

Open SPI MOSI Shift Register in the HDLForge interactive editor.

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• Parameterized PWM Generator — Easy
• Toggle-Based Pulse Synchronizer — Hard
• Clock-Enable Data Register — Easy

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