Four-Sample Delay Line
Store the current and previous input samples for a four-tap FIR.
Task
On each valid sample, shift the delay line so `x0` is newest and `x3` is oldest.
Examples
- First valid sample appears at x0.
- Each following sample pushes older values toward x3.
Constraints
- Shift only when `sample_valid` is high.
- Clear all taps on reset.
- Use signed 16-bit samples.
What this problem is testing
FPGA problems test whether logically correct RTL will behave predictably in hardware, including clock-domain boundaries, reset release, noisy inputs, inferred resources, and timing.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Separate functional checks from implementation concerns such as CDC and timing.
- Test asynchronous or noisy inputs with realistic transitions when relevant.
- Confirm reset assertion and release do not create unintended pulses or state.
- Review whether the RTL infers the intended FPGA resource.
Common mistakes
- Treating an asynchronous input as synchronous.
- Using a simple synchronizer for a pulse or multi-bit bus when a different CDC structure is needed.
- Generating clocks in ordinary RTL when a clock enable would be safer.
- Ignoring implementation timing because behavioral simulation passes.
Interview follow-up questions
- What hardware-specific issue could make a simulation-only solution unreliable?
- What timing or CDC check would you review before sign-off?
Concepts to review
DSP, FIR, shift register
Open Four-Sample Delay Line in the HDLForge interactive editor.
Related problems
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- Traffic Light FSM — Easy
- Parameterized PWM Generator — Easy
- Toggle-Based Pulse Synchronizer — Hard
- Clock-Enable Data Register — Easy
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