Four-Tap FIR Datapath
Compute the combinational weighted sum for four delayed samples.
Task
Multiply four signed samples by four signed coefficients and sum the products into a wide signed result.
Examples
- All four taps contribute in the same cycle.
- Output width is wider than individual products.
Constraints
- Treat samples and coefficients as signed.
- Use all four products.
- Provide at least 35 result bits.
Accelerator verification checklist
- Exercise zero, maximum positive and negative operands where signed data is used.
- Check exact bit growth and make overflow or saturation behavior intentional.
- Verify reset, enable, valid and pipeline alignment cycle by cycle.
- Send back-to-back data to confirm the advertised throughput.
Concepts to review
DSP, FIR, parallel MAC
Open Four-Tap FIR Datapath in the HDLForge interactive editor.
Related problems
- Signed INT8 Multiply-Accumulate — Easy
- Four-Lane INT8 Dot Product — Medium
- Eight-Lane Reduction Adder — Medium
- ReLU with 8-bit Saturation — Medium
- Systolic Array Processing Element — Hard