DSP Valid Pipeline
Keep control timing aligned with a multi-stage arithmetic datapath.
Task
Delay `in_valid` by three clock cycles and expose the final pulse as `out_valid`.
Examples
- in_valid at cycle N → out_valid at N+3.
- reset clears all validity state.
Constraints
- Use a 3-bit shift register or equivalent.
- Synchronous reset.
- One clock of latency per stage.
What this problem is testing
FPGA problems test whether logically correct RTL will behave predictably in hardware, including clock-domain boundaries, reset release, noisy inputs, inferred resources, and timing.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Separate functional checks from implementation concerns such as CDC and timing.
- Test asynchronous or noisy inputs with realistic transitions when relevant.
- Confirm reset assertion and release do not create unintended pulses or state.
- Review whether the RTL infers the intended FPGA resource.
Edge cases worth testing
- An immediately preceding dependency.
- A dependency that can be forwarded versus one that requires a stall.
Common mistakes
- Treating an asynchronous input as synchronous.
- Using a simple synchronizer for a pulse or multi-bit bus when a different CDC structure is needed.
- Generating clocks in ordinary RTL when a clock enable would be safer.
- Ignoring implementation timing because behavioral simulation passes.
Interview follow-up questions
- What hardware-specific issue could make a simulation-only solution unreliable?
- What timing or CDC check would you review before sign-off?
Concepts to review
DSP, pipeline, valid
Open DSP Valid Pipeline in the HDLForge interactive editor.
Related problems
- Button Debouncer — Easy
- Traffic Light FSM — Easy
- Systolic Array Processing Element — Hard
- Valid-Tagged Pipelined Multiplier — Hard
- Ready/Valid Skid Buffer — Hard
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