Clock-domain crossing / FPGA / ASIC

Asynchronous FIFO and CDC Guide

An asynchronous FIFO moves ordered data between unrelated clocks by keeping the memory local while synchronizing pointer information across domains. The difficult part is not the RAM—it is representing multi-bit pointer state safely, comparing synchronized pointers correctly and making reset behavior deterministic in both domains.

Core design rules

• Maintain binary pointers locally for addressing and derive Gray-code pointers for clock-domain crossing.
• Synchronize Gray pointers through two-flop chains before using them in the opposite clock domain.
• Generate empty in the read domain and full in the write domain using only locally clocked state plus synchronized remote pointers.
• Treat reset deassertion as a CDC problem: asynchronous assertion with synchronous release is a common robust pattern.

Implementation path

• Build and test binary-to-Gray conversion independently.
• Add reset synchronizers for each domain and document the reset assumptions.
• Implement pointer synchronizers, then empty detection, then full detection.
• Only after the control path is proven should you combine it with the dual-port memory datapath.

Verification checklist

• Use different, non-harmonically related write/read clock periods.
• Sweep from write-faster-than-read to read-faster-than-write conditions.
• Reset one or both domains around empty/full boundaries and inspect recovery.
• Assert that overflow/underflow are impossible and that dequeued data preserves enqueue order.

Useful RTL / verification pattern

// Binary to Gray
gray = binary ^ (binary >> 1);
// Cross Gray pointers through synchronizer flops, not raw binary counters.

Practice with executable problems

Turn it into a project